SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

4.3.3 Abs2Qep High Level Controller (HLC)

The high level controller is programmed to:

  • Start the PTO signal generation
  • Modify the HALT / CLEAR_LATCH and PTO_DONE signals
  • Load the counter match values required to generate a PTO
  • Tag an end of PTO state

Table 4-8 Abs2Qep HLC Register Usage
R0 and R1 Used to PULL data from the FIFO.
R2 Initialized to zero during CLB configuration. Used to load zero to a match reference in order to manipulate a given signal to a high state.
R3 Initalized to 0xFFFFFFFF during CLB configuration. Used to load a large value to a match reference in order to manipulate a given signal to a low state.
Table 4-9 Abs2Qep HLC Programs
LOAD: Event 0, Event 1
Instruction # Opcode(s) Description
Program0: 0 MOV_T1 R2, C1 Assert HALT/CLEAR_LATCH. COUNTER 1 has been reset by PTO_DONE (count == 0). Loading a match1 reference of zero will force a rising edge on HALT/CLEAR_LATCH.
Program0: 1 MOV_T2 R3, C1 Force the PTO_DONE signal low.
Program0: 2, 3 PULL R0
MOV_T2 R0, C1		 Load the number of QCLKs to be generated.
Note: for a case of zero QCLKs: since COUNTER_1 count == 0, a QCLK value of zero will force PTO_DONE back to a high state.
Program0: 4, 5 PULL R1
MOV_T2 R0, C0		 Load the number of CLB clocks between two QCLKs. When the counter reaches this value, it will be reset to zero.
Program0: 6, 7
Program1: 0, 1		 PULL R0
MOV_T1 R0, C2
PULL R0
MOV_T2 R0, C2		 Configure which QCLK edge will force PTO-QEP-I high and low. A large value will be passed through the FIFO if PTO-QEP-I should remain low.
Program1: 2 MOV R1, C0 Set COUNTER_0 to zero. This prevents the counter from incrementing by 1 when a zero pulse configuration is loaded.
Program1: 3 INTR 1 Tag indicates Event 0 plus Event 1 complete. This is placed next to the last instruction to keep it from being back-to-back with the INTR instruction in Event 2.
Program1: 4 MOV_T1 R3, C1 Force the HALT / CLEAR_LATCH signal low. This will start PTO signal generation if the PTO_DONE signal is low. If PTO_DONE is high, then the HALT_LATCH will be set.
PTO_DONE: Event 2
Instruction # Opcode(s) Description
Program2: 0 INTR 2 Tag to indicate Event 2 is complete or that the PTO has finished.