SPRAC77E January   2022  – February 2022 TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Trademarks
  2. 1Introduction
  3. 2PTO – PulseGen
    1. 2.1 PulseGen Implementation Overview
    2. 2.2 PulseGen Limitations
    3. 2.3 PulseGen CLB Configuration
    4. 2.4 PulseGen Input and Output Signals
  4. 3PTO – QepDiv
    1. 3.1 QepDiv Implementation Overview
    2. 3.2 QepDiv Limitations
    3. 3.3 QepDiv Divider Settings and Initialization
    4. 3.4 QepDiv CLB Configuration
  5. 4PTO – Abs2Qep
    1. 4.1 Abs2Qep Chip resources
    2. 4.2 Abs2Qep Theory of Operation
      1. 4.2.1 Abs2Qep Translation Equations
      2. 4.2.2 Abs2Qep Translation Example
      3. 4.2.3 Abs2Qep Zero Cross Detection
    3. 4.3 Abs2Qep CLB Configuration
      1. 4.3.1 Abs2Qep QEP-A/B Pulse Train Generation
      2. 4.3.2 Abs2Qep Halt Latch
      3. 4.3.3 Abs2Qep High Level Controller (HLC)
    4. 4.4 Abs2Qep Input and Output Signals
  6. 5PTO – QepOnClb QEP Decoder
    1. 5.1 QepOnClb and eQEP Comparison
    2. 5.2 QepOnClb Chip resources
    3. 5.3 QepOnClb Theory of Operation
    4. 5.4 QepOnClb CLB Resources
      1. 5.4.1 QepOnClb QCLK State Machine
      2. 5.4.2 QepOnClb Direction Decode
      3. 5.4.3 QepOnClb Error Detection
      4. 5.4.4 QepOnClb Simulation Waveforms
  7. 6Example Projects
    1. 6.1 Hardware Requirements
    2. 6.2 Installing Code Composer Studio and C2000WARE-MOTORCONTROL-SDK™
    3. 6.3 Import and Run Example Project
    4. 6.4 PulseGen Example
    5. 6.5 QepDiv Example
    6. 6.6 Abs2Qep Example
      1. 6.6.1 Watch Variables
      2. 6.6.2 Test Signals
      3. 6.6.3 Pin Usage and Test Connections
    7. 6.7 QepOnClb Example
      1. 6.7.1 Watch Variables
      2. 6.7.2 Header Pin Connections
  8. 7Library Source and Projects
    1. 7.1 Locating the Library Source Code
    2. 7.2 Import and Build the Library Project
    3. 7.3 PTO - PulseGen API
      1. 7.3.1 pto_pulsegen_runPulseGen
      2. 7.3.2 pto_startOperation
      3. 7.3.3 pto_pulsegen_setupPeriph
      4. 7.3.4 pto_pulsegen_reset
    4. 7.4 PTO - QepDiv API
      1. 7.4.1 pto_qepdiv_config
      2. 7.4.2 pto_startOperation
      3. 7.4.3 pto_qepdiv_setupPeriph
      4. 7.4.4 pto_qepdiv_reset
    5. 7.5 PTO - Abs2Qep API
      1. 7.5.1 Abs2Qep API Configuration
      2. 7.5.2 pto_abs2qep_runPulseGen
      3. 7.5.3 pto_abs2qep_setupPeriph
      4. 7.5.4 pto_abs2qep_translatePosition
    6. 7.6 PTO - QepOnClb API
      1. 7.6.1 pto_qeponclb_setupPeriph
      2. 7.6.2 pto_qeponclb_initCLBQEP
      3. 7.6.3 pto_qeponclb_configMaxCounterPos
      4. 7.6.4 pto_qeponclb_enableCLBQEP
      5. 7.6.5 pto_qeponclb_resetCLBQEP
      6. 7.6.6 pto_qeponclb_getCounterVal
      7. 7.6.7 pto_qeponclb_getCLBQEPPos
      8. 7.6.8 pto_qeponclb_clearFIFOptr
  9. 8Using the Reference APIs in Projects
    1. 8.1 Adding PTO Support to a Project
    2. 8.2 Routing To and From the CLB
    3. 8.3 Initialization Steps
      1. 8.3.1 PTO-PulseGen API Initalization
      2. 8.3.2 PTO-QepDiv API Initialization
      3. 8.3.3 PTO-Abs2Qep API Initialization
      4. 8.3.4 PTO-QepOnClb API Initialization
  10. 9References
  11.   Revision History

6.5 QepDiv Example

The test inputs and the PTO outputs are routed internally as shown in the mapping tables. The code that routes the signals can be found in the functions listed in Table 6-4.

Table 6-4 QepDiv Example Input/Output Signal Routing
Function Location Notes
Input Signal Routing: GPIO to CLB
pto_qepdiv_setup_GPIO() Example application Connect input GPIO to an INPUTXBAR.
pto_qepdiv_initCLBXBAR() Library Route INPUTXBARs to the global CLB AUXSIGx signals.
pto_qepdiv_setupPeriph() Library Connect tile inputs to the CLB global MUX, CLB local MUX or the tile's GPREG.
Output Routing: CLB to GPIO
Function Location Notes
pto_qepdiv_initCLBXBAR Library Connect tile's out4 or out5 to OUTPUTXBAR
pto_qepdiv_startOperation() Library Enable CLB output to override peripheral signals via setOutputMask()
pto_qepdiv_setup_GPIO() Example application Connect GPIO output to a peripheral or an OUTPUTXBAR

Table 6-5 F28002x, F28003x, F28004x, F2837x and F2838x QepDiv Output GPIO Mapping
QepDiv Input QepDiv Output
Input Signal Connect to for Demo (1) Routing to CLB Output Signal Routing From the CLB GPIO Pin
QEP-A: GPIO10 EPWM4A/GPIO6
or External Signal		 INPUTXBAR4 →
AUXSIG0 →
Tile1 in1, in2 and
Tile2 in1, in2		 PTO_QEP-A Override PWM2A GPIO2
QEP-B: GPIO11 EPWM5A/GPIO8
or External Signal		 INPUTXBAR5 →
AUXSIG1 →
Tile1 in4, in5 and
Tile2 in4		 PTO_QEP-B Override PWM2B GPIO3
QEP-I: GPIO9 EPWM4B/GPIO7
or External Signal		 INPUTXBAR6 →
AUXSIG2 →
Tile1 in7		 PTO_QEP-I Tile1 out5 → OUTPUTXBAR3 GPIO5
(1) In the example, spare EPWMs are used to provide QEP inputs. These are for test purposes and do not correspond to real-time usage. You can choose to connect these EPWM outputs to the QepDiv input signals or you can choose to connect other external signals.

Table 6-6 lists the connections that need to be made to use the EPWMs as inputs to QepDiv.

Table 6-6 QepDiv Test Input Connections
Board EPWM4A to QEP-A EPWM5A to QEP-B EPWM4B to QEP-I
LAUNCHXL-F280025C 78 (IO.6) to 14 (IO.10) 76 (IO.16) to 15 (IO.11) 77 (IO.7) to 7 (IO.9)
LAUNCHXL-F280039C 78 (IO.6) to 36 (IO.10) 76 (IO.16) to 35 (IO.11) 77 (IO.7) to 7 (IO.9)
LAUNCHXL-F280049C 78 to 40 38 to 39 77 to 37
LAUNCHXL-F28379D 80 to 76 78 to 75 79 to 77
TMDSCNCD28388D 54 to 61 57 to 63 56 to 59