Does your design have the proper connections for the type of
DDR that you have selected? The AM65x uses the same pins to support
DDR3, DDR4, and LPDDR4, but these standards have different names for the signals
connected to the memory device. The DRSS0 AC Bus Mapping table in the
AM65x Multicore ARM Keystone III SoC Technical Reference
Manual provides a mapping of the DDR pin names on the device to
the appropriate signal name for each memory type.
Do you have notes in you schematic or guidelines to ensure
that the DDR routing is done properly? It is very important to follow
the DDR routing guidelines in the AM65x device data sheet. These guidelines are
very important to ensure a proper DDR operation. Failure to follow these
guidelines will result in a nonfunctional DDR interface.
Does your design include the correct amount of decoupling
for the DDR interface? Always provide adequate decoupling capacitors on
the DDR power rails both at the AM65x/DRA80x device and at the DDR SDRAM device.
Proper distribution of these capacitors is mandatory when referencing fly-by
signals to VDDS.
Have you connected the DDR RESET signal correctly for the
type of device you have selected? DDR RESET signal is treated
differently from other control signals. Review the device data manual for proper
operation. The addition of a pull-down resistor is also recommended.
Did you include the proper termination for the DDR memory
device you have selected? DDR3 and DDR4 have specific requirements for
the termination of the flyby signals. Ensure that your signals are terminated
correctly for the device selected. LPDDR4 does not use fly-by routing and it
does not require VTT termination.
Did you include decoupling only
for the DDR_VREF0 signal? VREF can be obtained from the VTT termination
regulator or from a resistor divider (2.2K-Ω 1% resistors) with capacitive
decoupling to ground. It may be used for the VREF signals on the DDR memory
devices, but should not be connected to the DDR_VREF0 signal on the
AM65x/DRA80x. The VREF voltage for the AM65x/DRA80x device is generated
internally. The DDR_VREF0 pin is used for external decoupling capacitors.
If your design supports ECC memory, does it have the
correct component? The AM65x/DRA80x supports 7 bits of ECC for x32-bit
architectures and 6 bits of ECC for x16-bit architectures. Generally, the same
device should be used for the ECC bits, even if some of the bits are
unused.
Have you kept the signals associated with a byte lane in a
group? Data bit swapping within the data byte is allowed with the
exception of the least significant bit, sometimes referred to as the prime bit.
DDR D0, D8, D16, and D24 must be connected to the least significant bit for each
byte on the memory device. The PHY is implemented such that this does not impact
leveling. Bit swapping is not allowed for any other group of signals, including
ADDR and CNTL.
Are you only using a single rank in your design? The
AM65x only supports single-rank operation. Signals for the second rank should
not be used.
Have you terminated unused DDR signals correctly? If a
portion of the DDR interface is not used, then the applicable DDRx_DQSn and
DDRx_DQSNn pins should be tied to the appropriate GND or power through a 1K-Ω
resistor to keep the signals inactive as described in the AM654x Sitara™
Processors Data Manual. The same is also required if only a
single byte lane is unused, such as the ECC byte lane. The address, command,
control, clock, and data lines can all be left floating. The DDR supplies and
VREF must be maintained at their rated levels per the AM654x Sitara™
Processors Data Manual.