SPRACI9A October   2018  – July 2021 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   Trademarks
  2. 1Introduction
  3. 2Recommendations Specific to the AM65x/DRA80x
    1. 2.1  EVM versus Data Sheet
    2. 2.2  Power
    3. 2.3  Reset
    4. 2.4  Boot Modes
    5. 2.5  Unused Signals
    6. 2.6  Clocking
    7. 2.7  System Issues
    8. 2.8  Low Power Considerations
    9. 2.9  DDR
    10. 2.10 MMC
    11. 2.11 OSPI and QSPI
    12. 2.12 GPMC NAND
    13. 2.13 I2C
    14. 2.14 CPSW Ethernet
    15. 2.15 ICSSG
    16. 2.16 USB
    17. 2.17 SERDES - USB3
    18. 2.18 SERDES - PCIe
    19. 2.19 JTAG and EMU
  4. 3References
  5. 4Revision History

2.11 OSPI and QSPI

  • Is the MCU_OSPI[x]_LBCLKO signal connected correctly for the device you have selected? The MCU_OSPI[x]_LBCLKO signal is used differently depending on what type of device you are using and if internal pad loopback is used.
  • Are the OSPI/QSPI data bits connected in the proper order? D0 and D1 of the OSPI peripheral must be connected to D0 and D1 of the QSPI/OSPI memory to support legacy x1 commands. TI does not support bit swapping on the balance of the data bits, so these must also be connected in the correct order.