This method is more complex than the duty cycle compensation because it is implemented with asymmetric PWM. It means that both CMPA and CMPB values in ePWM module should be updated with different value depending on the value to be shifted. This method has some advantage such as same output voltage with original output voltage command. Also, it can be widely used in many applications because it doesn’t rely on any motor and system parameters, even though it has some disadvantage such as high THD and acoustic noise than the two- or three-shunt solution.

If dc link currents are sampled at PWM down count such as Figure 2-12, V1 and V2 vector duration on right side of SVPWM should have enough large than minimum active duration. To do this, first, find maximum and minimum duty cycle. The maximum duty cycle is shifted to the right direction to get a minimum active duration if the V1 vector between maximum and middle duty cycle is less than the minimum active duration get in Equation 2. Also, the minimum duty cycle is shifted to the left direction to get a minimum active duration if the V2 vector between middle and minimum duty cycle is less than the minimum active duration. The PWM channel with midrange duty cycle remains unchanged. Figure 3-3 shows the PWM phase shift compensation method explained above.

Figure 3-4 shows the software flowchart of this method including ADC sampling point calculation. The CMPA and CMPB in EPWMx are newly calculated to have minimum active duration. It is necessary to know which sector the voltage reference output is in to determine which PWM channel have to be updated. Equation 4 shows the equation that was introduced in Space-Vector PWM with TMS320C24x/F24x Using Hardware and Software Determined Switching Patterns to determine the sector.