SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The main constraint in determining layer count is the number of layers required to implement the high speed DDR4/LPDDR4 interface. It may be possible to reduce the layer count in comparison to the EVM or the SK. Refer the AM64x / AM243x DDR Board Design and Layout Guidelines application note available on TI.com for further guidance and best practices in implementing the DDR4/LPDDR4 interface on custom design.