SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Many of the TI EPHYs configure their outputs as inputs during reset, and captures configuration (Pin strapping is done through resistors) information on these inputs when the processor is released from reset. It may be necessary to apply appropriate pullup or pulldown resistors on these inputs (IOs) which also connect to processor IOs. TI EPHYs used on the EVM or SK use a combination of pullup and pulldown resistors allowing multiple configuration modes to be configured using each pin. By default, the processor input buffers and internal pullup or pulldown resistors are disabled, which minimizes any concern of a mid-supply potential being applied to the processor input buffer by the EPHY. The EPHYs are required to be configured to normal state from reset state to ensure the EPHY is driving a valid logic state before enabling any of the associated processor input buffers.