SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
USB3.0 interface includes SuperSpeed (SS) USB 3.0 Dual-Role Device (DRD) subsystem with on-chip SS (USB3.0) PHY and HS/FS/LS (USB2.0) PHY.
SERDES0 PHY Differential Transmit Data (TX0) and Differential Receive Data (RX0) signals are configured for USB3.0 functionality. SERDES0_TX0_P and SERDES0_TX0_N are configured as USB0_SSTXP and USB0_SSTXN. SERDES0_RX0_P and SERDES0_RX0_N are configured as USB0_SSRXP and USB0_SSRXN.