SPRACV1B February   2022  – January 2024 AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Abstract
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Core Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 Trigonometric Functions
  6. 3Compute and Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
      3. 3.1.3 Cortex-R5 Memory Access Latency
    2. 3.2 CoreMark®-Pro
    3. 3.3 Fast Fourier Transform
    4. 3.4 Cryptographic Benchmarks
  7. 4Application Benchmarks
    1. 4.1 Machine Learning Inference
    2. 4.2 Field Oriented Control (FOC) Loop
    3. 4.3 PCIE to DDR Performance Using BCDMA
      1. 4.3.1 Test Setup
      2. 4.3.2 Result and Observation
    4. 4.4 DDR to DDR Performance Using BCDMA
      1. 4.4.1 Test Setup
      2. 4.4.2 Result and Observation
  8. 5References
  9. 6Revision History

1 Introduction

The benchmarks were measured on the Cortex®-A53 and Cortex-R5F cores. For up to date results, refer to the Performance Guide and the Benchmark Demo application in the Processor SDK for AM64x. The benchmarking was produced using the following: TMDS64GPEVM, SK-AM64X, and LP-AM243. The key board parameters for the evaluation were 1GHz clock speed for the Cortex-A53 cores, 800MHz for the Cortex-R5F cores, and a 16-bit wide DDR4 or LPDDR4 at a speed of 1600MT/s. AM64x adds a dual core Cortex-A53 including a 256kB L2 cache, but otherwise the devices are identical. For reference, see Figure 1-1 and Figure 1-2.

GUID-954DDF66-F404-476D-96B3-51181A6CF04F-low.gif
A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across SoC when in non-isolated configuration.
Figure 1-1 Functional Block Diagram: AM64x
GUID-20201201-CA0I-NC01-GNLX-VDTJ0GX0BWZ0-low.gif Figure 1-2 Functional Block Diagram: AM243x