SPRACX9 July   2021 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Jacinto 7 Imaging Subsystem Overview
  3. 2Camera Capture Subsystem
    1. 2.1 MIPI-CSI2
    2. 2.2 The Video Processing Front End
  4. 3The Vision Pre-Processing Accelerator
    1. 3.1 Video Imaging Subsystem (VISS)
    2. 3.2 Lens Distortion Correction (LDC)
    3. 3.3 Multi-Scalar (MSC)
    4. 3.4 Bilateral Noise Filtering (BNF)
    5. 3.5 Software Availability for Camera Sensors
  5. 4Example Use-Cases
    1. 4.1 4x Camera Use-Case With MIPI Aggregator
    2. 4.2 Generic 8-Camera Use-Case
    3. 4.3 ADAS Use Case
  6. 5References

2.2 The Video Processing Front End

The Video Processing Front End (VPFE) is an input interface module that receives raw image/video data or YUV digital video data from external imaging peripherals such as image sensors. VPFE supports following features:

  • Support for conventional Bayer pattern and Foveon sensor formats.
    • Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator
    • Support for progressive (non-interlaced) and interlaced sensors
    • Support for up to 110-MHz sensor clock.
    • Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit).
    • Support for YCbCr 422 format, either 8- or 16-bit with discrete HSYNC and VSYNC signals.
    • Support for up to 16-bit input.