SPRACX9 July   2021 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Jacinto 7 Imaging Subsystem Overview
  3. 2Camera Capture Subsystem
    1. 2.1 MIPI-CSI2
    2. 2.2 The Video Processing Front End
  4. 3The Vision Pre-Processing Accelerator
    1. 3.1 Video Imaging Subsystem (VISS)
    2. 3.2 Lens Distortion Correction (LDC)
    3. 3.3 Multi-Scalar (MSC)
    4. 3.4 Bilateral Noise Filtering (BNF)
    5. 3.5 Software Availability for Camera Sensors
  5. 4Example Use-Cases
    1. 4.1 4x Camera Use-Case With MIPI Aggregator
    2. 4.2 Generic 8-Camera Use-Case
    3. 4.3 ADAS Use Case
  6. 5References

3 The Vision Pre-Processing Accelerator

The Vision Pre-processing Accelerator (VPAC) subsystem is a set of common vision primitive functions, performing pixel data processing tasks, such as: color processing and enhancement, noise filtering, wide dynamic range (WDR) processing, lens distortion correction, pixel remap for de-warping, on-the-fly scale generation, and on-the-fly pyramid generation. The VPAC offloads these common tasks from the main SoC processors (ARM, DSP, and so forth), so these CPUs can be utilized for differentiated high-level algorithms. The VPAC is designed to support multiple cameras by working in time-multiplexing mode. The VPAC works as a front end to vision processing pipeline and provides for further processing by other vision accelerators or processor cores inside the SoC.

Figure 3-1 shows the VPAC high-level block diagram.

GUID-20210615-CA0I-FTHF-VKKL-J4MFRXSDRQVK-low.gif Figure 3-1 VPAC Block Diagram

The VPAC is composed on following major blocks:

  • Video Imaging Subsystem (VISS)
  • Lens Distortion Correction (LDC)
  • Bilinear Noise Filter (BNF)
  • Multi-scaler (MSC)