SPRAD06B March   2022  – November 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  DBI
    8. 2.8  VPP
    9. 2.9  Net Classes
    10. 2.10 DDR4 Signal Termination
    11. 2.11 VREF Routing
    12. 2.12 VTT
    13. 2.13 POD Interconnect
    14. 2.14 CK and ADDR_CTRL Topologies and Routing Guidance
    15. 2.15 Data Group Topologies and Routing Guidance
    16. 2.16 CK and ADDR_CTRL Routing Specification
      1. 2.16.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.16.2 CK and ADDR_CTRL Routing Limits
    17. 2.17 Data Group Routing Specification
      1. 2.17.1 DQLM - DQ Longest Manhattan Distance
      2. 2.17.2 Data Group Routing Limits
    18. 2.18 Bit Swapping
      1. 2.18.1 Data Bit Swapping
      2. 2.18.2 Address and Control Bit Swapping
  6. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  LPDDR4 DBI
    8. 3.8  Net Classes
    9. 3.9  LPDDR4 Signal Termination
    10. 3.10 LPDDR4 VREF Routing
    11. 3.11 LPDDR4 VTT
    12. 3.12 CK0 and ADDR_CTRL Topologies
    13. 3.13 Data Group Topologies
    14. 3.14 CK0 and ADDR_CTRL Routing Specification
    15. 3.15 Data Group Routing Specification
    16. 3.16 Byte and Bit Swapping
  7. 4LPDDR4 Board Design Simulations
    1. 4.1 Board Model Extraction
    2. 4.2 Board-Model Validation
    3. 4.3 S-Parameter Inspection
    4. 4.4 Time Domain Reflectometry (TDR) Analysis
    5. 4.5 System Level Simulation
      1. 4.5.1 Simulation Setup
      2. 4.5.2 Simulation Parameters
      3. 4.5.3 Simulation Targets
        1. 4.5.3.1 Eye Quality
        2. 4.5.3.2 Delay Report
        3. 4.5.3.3 Mask Report
    6. 4.6 Design Example
      1. 4.6.1 Stack-Up
      2. 4.6.2 Routing
      3. 4.6.3 Model Verification
      4. 4.6.4 Simulation Results
  8. 5Appendix: AM62x ALW and AMC Package Delays
  9. 6Revision History

3.14 CK0 and ADDR_CTRL Routing Specification

Skew within the CK0 and ADDR_CTRL net classes directly reduces setup and hold margin for the ADDR_CTRL nets. Thus, this skew must be controlled. Per-bit deskew capability within the PHY substantially loosens the skew tolerance requirements. The skew budgets in Table 3-6 include total delay from SoC die pad to DRAM pin. (i.e. delay of SOC package + PCB). Package delays are provided in Appendix: AM62x ALW and AMC Package Delays. The designer is free to length match using smaller tolerance than the values shown in the table. The routed PCB track has a delay proportional to its length. Thus, the delay skew must be managed through matching the lengths of the routed tracks within a defined group of signals. The only way to practically match lengths on a PCB is to lengthen the shorter traces. Consider Z-axis delays (VIAs) with accurate stackup information during analysis.

Table 3-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK0 and ADDR_CTRL topology diagram shown previously in Figure 3-4 and Figure 3-5. By matching the length for the same segments of all signals in a routing group, the signal delay skews are controlled. Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

Table 3-6 CK0 and ADDR_CTRL Routing Specifications
Number Parameter MIN TYP MAX UNIT
LP4_ACRS1 Propagation delay of net class CK0
(RSAC1)		 450(1) ps
LP4_ACRS2 Propagation delay of net class ADDR_CTRL
(RSAC2)		 450(1) ps
LP4_ACRS3 Skew within net class CK0 (Skew of DDR0_CK0 and DDR0_CK0_n)
(RSAC1)		 0.75(2)(3) ps
LP4_ACRS6 Skew across ADDR_CTRL and CK0 clock net classes, relative to propagation delay of CK0 net class
(RSAC1 - RSAC2)(4)		 -312.5(3)(5) 312.5(3)(5) ps
LP4_ACRS7 Vias per trace 3(1) vias
LP4_ACRS8 VIA Stub Length 20 Mils
LP4_ACRS9 Via count difference 1(6) vias
LP4_ACRS10 Center-to-center CK0 to other LPDDR4 trace spacing 5w(7)
LP4_ACRS11 Center-to-center ADDR_CTRL to other LPDDR4 trace spacing 5w(7)
LP4_ACRS12 Center-to-center ADDR_CTRL to self or other ADDR_CTRL trace spacing 3w(7)
LP4_ACRS13 CK0 center-to-center spacing(8) See note below
LP4_ACRS14 CK0 spacing to non-DDR net 5w(7)
(1) Max value is based upon conservative signal integrity approach. FR4 material assumed with Dk ~ 3.7 - 3.9 & Df ~ 0.002. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) Recommendation for PCB layout tool design. Required to be verified by simulation(9), confirm JEDEC defined Vix_DQS_ratio (20%) and Vix_CK_ratio (25%) are satisfied, also confirm good eye margins.
(3) Consider the delays from SOC die pad to the DRAM pin (ie. delays of SOC package + delays of PCB upto the DRAM pin. DRAM package delays are omitted). Refer to Appendix: AM62x ALW and AMC Package Delays.
(4) Recommend routing net classes CK0 and ADDR_CTRL on same signal layer for better skew control.
(5) Simulation(9) must be performed and the delay report analyzed to ensure delays are within the limit. Delay reports from PCB layout tools use a simplified calculation based on a constant propagation velocity factor. TI recommends initially delay matching in PCB layout tool to a target less than 20% of the limit.
(6) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
(7) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints). Spacing minimums may be relaxed if simulations(9) accurately capture crosstalk between neighboring victim and aggressor traces and show good margin. Consider also VIA spacing. Signals with adjacent VIAs near SOC should not also have adjacent VIAs near the DRAM.
(8) P to N spacing set to ensure proper differential impedance. The designer must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer. Refer to impedance targets in Table 1-1
(9) Simulation refers to a power-aware IBIS Signal Integrity (SI) simulation. Simulate across process, voltage, and temperature (PVT). Refer to LPDDR4 Board Design Simulations