SPRAD06B March   2022  – November 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  DBI
    8. 2.8  VPP
    9. 2.9  Net Classes
    10. 2.10 DDR4 Signal Termination
    11. 2.11 VREF Routing
    12. 2.12 VTT
    13. 2.13 POD Interconnect
    14. 2.14 CK and ADDR_CTRL Topologies and Routing Guidance
    15. 2.15 Data Group Topologies and Routing Guidance
    16. 2.16 CK and ADDR_CTRL Routing Specification
      1. 2.16.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.16.2 CK and ADDR_CTRL Routing Limits
    17. 2.17 Data Group Routing Specification
      1. 2.17.1 DQLM - DQ Longest Manhattan Distance
      2. 2.17.2 Data Group Routing Limits
    18. 2.18 Bit Swapping
      1. 2.18.1 Data Bit Swapping
      2. 2.18.2 Address and Control Bit Swapping
  6. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  LPDDR4 DBI
    8. 3.8  Net Classes
    9. 3.9  LPDDR4 Signal Termination
    10. 3.10 LPDDR4 VREF Routing
    11. 3.11 LPDDR4 VTT
    12. 3.12 CK0 and ADDR_CTRL Topologies
    13. 3.13 Data Group Topologies
    14. 3.14 CK0 and ADDR_CTRL Routing Specification
    15. 3.15 Data Group Routing Specification
    16. 3.16 Byte and Bit Swapping
  7. 4LPDDR4 Board Design Simulations
    1. 4.1 Board Model Extraction
    2. 4.2 Board-Model Validation
    3. 4.3 S-Parameter Inspection
    4. 4.4 Time Domain Reflectometry (TDR) Analysis
    5. 4.5 System Level Simulation
      1. 4.5.1 Simulation Setup
      2. 4.5.2 Simulation Parameters
      3. 4.5.3 Simulation Targets
        1. 4.5.3.1 Eye Quality
        2. 4.5.3.2 Delay Report
        3. 4.5.3.3 Mask Report
    6. 4.6 Design Example
      1. 4.6.1 Stack-Up
      2. 4.6.2 Routing
      3. 4.6.3 Model Verification
      4. 4.6.4 Simulation Results
  8. 5Appendix: AM62x ALW and AMC Package Delays
  9. 6Revision History

2.16.2 CK and ADDR_CTRL Routing Limits

Table 2-6 lists the limits for the individual segments that comprise the routing from the processor to the SDRAM. These segment lengths coincide with the CK and ADDR_CTRL topology diagram shown previously in Figure 2-5 and Figure 2-6. By matching the length for the same segments of all signals in a routing group, the signal delay skews are controlled.

Recall that the CK and ADDR_CTRL nets route along the same path for each segment. This simplifies the length matching. The skew limits for the CK group compare the length of DDR0_CK0P to the length of DDR0_CK0N. Then the skew limits for the ADDR_CTRL group nets are compared to the CK group nets.

Most PCB layout tools can be configured to generate reports to assist with this validation. If this cannot be generated automatically, this must be generated and verified manually.

Table 2-6 also lists skew limits for the full routes from the processor to each SDRAM. This must be checked in addition to the skew limits in the individual sections to verify that there is not accumulating error in the layout.

To use length matching (in mils) instead of time delay (in ps), multiply the time delay (in ps) limit by 5. The microstrip routes propagate faster than stripline routes. A standard practice when using length matching is to divide the microstrip length by 1.1 to achieve a compensated length to normalize the microstrip length with the stripline length and to align with the delay limits provided. This is called velocity compensation (see Section 1.5).

Table 2-6 CK and ADDR_CTRL Routing Specifications
Number Parameter MIN TYP MAX UNIT
1 A1+A2 length 500 (1) ps (12)
2 A1+A2 skew ADDR_CTRL to CK (4) 3 ps
4 A3 skew ADDR_CTRL to CK (4) 3 ps
3 A3 length 125 ps
5 A1+A2 skew DDR0_CK0 to DDR0_CK0_n 0.4 ps
6 A3 skew DDR0_CK0 to DDR0_CK0_n 0.4 ps
7 AS length 5 (1) 17 ps
8 AS skew 1.3 (1) 3 ps
9 AS+/AS- length 5 17 ps
10 AS+/AS- skew 0.4 ps
11 AT length (3) 75 ps
12 AT skew ADDR_CTRL to CK (4) 14 ps
13 AT skew DDR0_CK0 to DDR0_CK0_n 0.4 ps
14 Total DDR0_CK0 to DDR0_CK0_n skew from processor to each SDRAM (2) 0.8 ps
15 Total CK to ADDR_CTRL skew from processor to each SDRAM (2) 4 ps
16 Vias per trace (11) 3(1) vias
17 Via count difference(11) 1(10) vias
18 Center-to-center CK to other DDR4 trace spacing(5) 4w
19 Center-to-center ADDR_CTRL to other DDR4 trace spacing(5) 4w
20 Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(5) 3w
21 CK center-to-center spacing(6)(7)

See notes below
22 CK spacing to other net(5) 4w
23 Rcp(8) Zo-1 Zo Zo+1 Ω
24 Rtt(8)(9) Zo-5 Zo Zo+5 Ω
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
(2) This is the combined length from the processor to the SDRAM. It must be computed for each SDRAM to ensure that the segment matching does not result in accumulated error. For the first SDRAM, it is A1 + A2 + AS, computed for each signal. For the 2nd SDRAM, it is A1 + A2 + A3 + AS, computed for each signal.
(3) While this length can be increased for convenience, its length should be minimized.
(4) ADDR_CTRL net class relative to its CK net class.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length (only near endpoints).
(6) CK spacing set to ensure proper differential impedance.
(7) The user must control the impedance so that inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the single-ended impedance, Zo, on that layer.
(8) Source termination (series resistor at driver) is specifically not allowed.
(9) Termination values should be uniform across the net class.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
(11) Count vias individually from processor to each SDRAM.
(12) PCB track length shown as ps is a normalized representation of length. 1 ps can be equated to 5 mils as a simple transformation. This is stripline equivalent length where velocity compensation must be used for all segments routed as microstrip track.