SPRAD20 March 2022 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The software resolver to digital converter is implemented with ADC, DMA and DAC configured in Section 2.2.2 and Section 2.2.3. An overview of the configuration is summarized in Figure 2-41. In this work, PWM X is EPWM0 and PWM Y is EPWM7. EPWM0 at 10kHz is the one triggering phase A power switches and the source of synchronization. EPWM7 at 20kHz is dedicated to trigger EDMA0 for resolver excitation via DAC. ADC Start Of Conversion (SOC) is triggered at EPWM0 count zero. End Of Conversion (EOC) of ADC4 is the source of ADC INT1 containing the FOC loop. This section is to present functions and readings of the software resolver.