SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
For availability of the PRUSS features and supported functionalities, refer the Device Comparison section of the device-specific data sheet.
The programmable nature of the PRU cores, along with their access to pins, events and all processor resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.
The PRUSS has a large number of IO signals available. Most of these IOs are multiplexed with other functional signals at the processor level. PRUSS pins allow muxing using the PADCONFIGx registers.
Review the interface connection supports the required functionalities during schematic design.
To understand the PRUSS supported functionalities, refer the device-specific data sheet and TRM.