General

Review and verify the following for the custom schematic design:

1. Above sections, including relevant application notes and FAQ links.
2. Pin attributes and signal description.
3. Electrical characteristics, timing parameters, and any additional available information.
4. MAC interface configuration and recommended connections including series resistors (on the TDn signals near to processor MAC TDn output pins and optional 0Ω series resistor near the attached device).
5. IO level compatibility between processor MAC and EPHY (attached device). The attached device IO supply and the IO supply group (IO supply rail) VDDSHV2 referenced by the interface signals are recommended to be connected to the same supply source.
6. Matching of processor and EPHY clock specifications.
7. Clocking of EPHY and processor MAC including addition of buffers based on the EPHY configuration and clock architecture (use of common Oscillator and Buffer or RMII interface). When the clock output connects to more than one inputs, each of the clock inputs must be buffered using individual buffers.
8. Interface connections, IO level compatibility, fail-safe operation (when MACs are powered by different power sources) and matching of clock specifications when MAC-to-MAC interface is used.
9. MDIO interface connection including pullup for MDIO data added near to the EPHY. MDIO connection to multiple devices and the addition of pullup near each EPHY.
10. When 2 EPHYs are used, configuration of EPHY device address to read the internal registers through the MDIO interface.
11. Implementation of EPHY reset logic. When 2 EPHYs are used, the recommendation is to provide provision to reset the EPHYs individually when used for boot a 2-3 input ANDing logic can be used.
12. In case implementing an Ethernet boot is required, verify the errata, supported EPHY interface configurations, MAC interface port used versus recommended, and the recommended clock and interface connection.

Schematic Review

Follow the below list for the custom schematic design:

1. Provision for series resistor for the processor MAC transmit signals TDx near to the processor output pins
2. Verify the EPHY reset implementation including ANDing logic, EPHY reset input pull and compare with SK as required
3. Verify EPHY device address configuration when 2 EPHYs are used and MDIO interface is required
4. Verify the IO level compatibility - the attached device IO supply and the IO supply group (IO supply rail) referenced by the processor interface signals are connected to the same supply source
5. Compare the bulk and decoupling capacitors used for all the EPHY supply rails with SK schematics when TI EPHY is used
6. Pullup is populated for processor GPIO input of the EPHY reset ANDing logic
7. Pullup on the MDIO clock may not be allowed (EPHY may have internal pulldown - verify in the data sheet)
8. Supply rails connected follow the ROC

Additional

1. Follow the below steps when TI EPHY is used:
   • Get the EPHY implementation reviewed by the relevant BU/PL
   • Verify the power sequence requirements for two-supply configuration and three-supply configuration
   • Verify the RBIAS resistor tolerance as per the EPHY data sheet
   • Selection of the RJ45 connector with integrated magnetics, follow SK
   • Provision for external ESD protection for the MDI signals
   • Connection of RJ45 connector shield to circuit ground
   • The recommended bulk and decoupling capacitors are provided (refer SK as required)
2. Use a single output, individual buffer device, or dual or multiple output buffer to connect the clock output of the oscillator to the processor and EPHYs. For specific use case (requirement for some of the industrial applications using a Time Sensitive Networking (TSN)) input and two or more output (based on number of EPHYs used) buffer is recommended for the processor and the EPHYs.
3. When EPHY is configured as RMII slave (peripheral), two-output phase aligned buffer with a common input is recommended.
4. If space is not a constraint, consider adding 0Ω series resistors on the RX signals near to the EPHY.
5. ANDing logic additionally performs level translation. Verify the reset IO level compatibility before optimizing the reset ANDing logic. IO level mismatch can cause supply leakage and affect processor operation.
6. To simplify the ANDing logic, use a 2-input AND gate with RESETSTATz and the processor IO as inputs.
7. Verify design recommendations as per the data sheet or EVM implementation are considered for the attached device, including terminations and external ESD protection.