General
Review and verify the following for
the custom schematic design:
- Above sections, including
relevant application notes and FAQ links
- Pin attributes, signal
description, and electrical specifications
- Electrical characteristics,
timing parameters, and any additional available information
- Connection of address, clock,
control and data signals - follow the processor-specific DDR design
guidelines
- DDR0_CAL0 and DDRSS IO pad
calibration resistor (240Ω, 1%) connected to VSS
- ZQ0-1, Memory device IO
calibration resistor (240Ω, 1%) connected to VDD_LPDDR4
- Memory device on-die
termination (ODT) pulled up through a resistor (2.2kΩ or similar, no
connection from DDRSS)
- Connection of chip select
CSn0-1
- For LPDDR4, x 16 is the
supported data bus width
- Connection of DDRSS RESETn
signal directly to LPDDR4_RESET_N memory reset input. To hold the signal low
during power-on initialization, add a pulldown (10kΩ) and placed near the
memory device
- Connection of DDRSS to 16-bit
memory device - refer DDR design guide
- Termination of unused DDRSS
interface signals as per DDR design guide
Schematic Review
Follow the below list for the custom
schematic design:
- Compare the bulk and
decoupling capacitors used and the values with SK schematics
- Value and tolerance used for
the calibration resistors
- Reset pulldown value and
connection of ODT pullup
- Memory selected confirms to
the JEDEC standards
- Supply rails connected follow
the ROC
Additional
- Add layout notes on the schematic
(for DDR routing to follow the recommended guidelines)