SPRAD44 june   2023 AM6442

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Required Hardware and Software
  6. 3AM6442 RTI Watchdog Modules
    1. 3.1 How the RTI Works in the U-Boot?
  7. 4About Those Six Commands in the U-Boot
  8. 5How to Turn These Commands Into C Code?
    1. 5.1 Entire RTI Patch for This Application Note
  9. 6References

3.1 How the RTI Works in the U-Boot?

By reading the device-specific TRM, here are six commands in the U-Boot prompt to get the RTI watchdog working:

  • mw.l 0x43009008 0x68EF3490 1
    (CTRL_MMR0, see AM64x/AM243x Technical Reference Manual)
  • mw.l 0x4300900C 0xD172BC5A 1
    (CTRL_MMR0, see TRM)
  • mw.l 0x43008380 0x3 1
    (CTRL_MMR0, see TRM)
  • mw.l 0xe0000a4 0xa 1
    (RTI0, see TRM)
  • mw.l 0xe000094 0x23 1
    (RTI0, see TRM)
  • mw.l 0xe000090 0xA98559DA 1
Note: The value 0x23 marked in red indicates the value you can configure for the watchdog expire value.

The flow is as follows:

  1. The first four commands are unlocking the Memory Mapped Register (MMR0) - MMR0 is used as an example. According to Table 3-1, you need to unlock the "MMR0 registers" for the RTI0.
  2. The 1st and 2nd commands are used for CTRL_MMR0 lock or unlock. For more details on CTRL_MMR0, see the Partition Unlock Values table in the Kick Protection Registers section in the AM64x/AM243x Technical Reference Manual.

    mw.l 0x43009008 0x68EF3490 1
    mw.l 0x4300900C 0xD172BC5A 1

  3. The 3rd cmd is to set the CTRLMMR_WWD0_CLKSEL Register, in which WWD0 is the window watchdog 0 = RTI0. The Value 0x3 is the 32K system clock source, according to the default setting. For more information, see the AM64x/AM243x Technical Reference Manual.

    mw.l 0x43008380 0x3 1

  4. The last 3 (4th, 5th, 6th) commands are used for configuring the RTI0.
    1. The 4th cmd is to set the RTI_WWDRXNCTR, Digital Windowed Watchdog Reaction. The value of this reg can only be either 0x5 or 0xa. 0xa was used for RTI generating non-maskable interrupt.

      mw.l 0xe0000a4 0xa 1

    2. The 5th cmd is to set the pre-load value, which is the timing window. This can be treated as an “Watchdog timeout expire value”.

      mw.l 0xe000094 0x23 1

    3. The 6th cmd is to enable the RTI watchdog:
      1. Value 0x5312ACED is to disable the RTI.
      2. Value 0xA98559DA is to enable the RTI.

      mw.l 0xe000090 0xA98559DA 1

Table 3-1 RTI Clocks and Resets
Module Instance Module Clock Input Source Clock Signal Source Description
RTI0 RTI0_ICLK MAIN_SYSCLK0/4 PLLCTRL0 RTI0 Interface Clock
RTI0_FCLK MCU_HFOSC0_CLKOUT MCU_HFOSC0 RTI0 Functional Clock. For more information about clock multiplexing in RTICLK0 MUX, see CTRLMMR_WWD0_CLKSEL [1:0] CLK_SEL in Control Module (CTRL_MMR).
MCU_HFOSC0_CLKOUT_32K
MCU_CLK_12M_RC MCU_RC_OSC_12M
CLK_32K
RTI1 RTI1_ICLK MAIN_SYSCLK0/4 PLLCTRL0 RTI1 Interface Clock
RTI1_FCLK MCU_HFOSC0_CLKOUT MCU_HFOSC0 RTI1 Functional Clock. For more information about clock multiplexing in RTICLK1 MUX, see CTRLMMR_WWD0_CLKSEL [1:0] CLK_SEL in Control Module (CTRL_MMR).
MCU_HFOSC0_CLKOUT_32K
MCU_CLK_12M_RC MCU_RC_OSC_12M
CLK_32K
RTI8 RTI8_ICLK MAIN_SYSCLK0/4 PLLCTRL0 RTI8 Interface Clock
RTI8_FCLK MCU_HFOSC0_CLKOUT MCU_HFOSC0 RTI8 Functional Clock. For more information about clock multiplexing in RTICLK8 MUX, see CTRLMMR_WWD0_CLKSEL [1:0] CLK_SEL in Control Module (CTRL_MMR).
MCU_HFOSC0_CLKOUT_32K
MCU_CLK_12M_RC MCU_RC_OSC_12M
CLK_32K