This section provides round-trip read latency measurements for processors in AM62x to various memory destinations in the system. The measurements where made on the AM62x platform using bare-metal silicon verification tests. The tests execute on A53, M4F and R5F processors out of LPDDR4. Each test includes a loop of 8192 iterations to read a total of 32 KiB of data. The number of cycles for each access were counted and divided by the respective processor clock frequency to obtain latency time. Table 3-4 shows the average latency results.

Tests were done at 0.75V VDD_CORE, 1.25Ghz A53 cores, 400MHz R5F core, 400MHz M4F cores, and 1600MT/s LPDDR4. Tightly-Coupled Memory, or TCM, is RAM that is directly attached to an ARM Cortex core. ARM architecture provides a local internal low latency path and also allows external access to the memory through SoC bus infrastructure.