SPRAD51A December   2023  – April 2024 TMS320F2800157 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28P659DK-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Programming Fundamentals
  6. 3ROM Bootloader and Hex Utility Usage
  7. 4DCAN Flash Kernel
    1. 4.1 Implementation
      1. 4.1.1 Custom Flash Bank and Sector Erase
      2. 4.1.2 Application Load
  8. 5MCAN Flash Kernel
    1. 5.1 Implementation
      1. 5.1.1 Custom Flash Bank and Sector Erase
      2. 5.1.2 Application Load
  9. 6Example Implementation
    1. 6.1 Device Setup
      1. 6.1.1 Flash Kernels
      2. 6.1.2 Hardware
    2. 6.2 Host Application: dcan_flash_programmer
      1. 6.2.1 Overview
      2. 6.2.2 Building and Running dcan_flash_programmer Using Visual Studio
      3. 6.2.3 Running dcan_flash_programmer for F28003x
      4. 6.2.4 Using the Project With DCAN Bootloader
      5. 6.2.5 Using the Project With CCS
    3. 6.3 Host Application: can_flash_programmer [MCAN]
      1. 6.3.1 Overview
      2. 6.3.2 Building and Running can_flash_programmer Using Visual Studio
      3. 6.3.3 Running can_flash_programmer for F28003x
      4. 6.3.4 Using the Project With MCAN Bootloader
      5. 6.3.5 Using the Project With CCS
    4. 6.4 Application Load: CPU2 Image
      1. 6.4.1 Combining Two Images (.txt)
  10. 7Troubleshooting
    1. 7.1 General
    2. 7.2 DCAN Boot
    3. 7.3 MCAN Boot
  11. 8References
  12. 9Revision History

4.1.2 Application Load

This section walks through the entire flow of programming an application into flash using the DCAN boot mode.

Ensure the device is ready for DCAN communications by resetting the device while ensuring the boot mode pins are in the proper state to select DCAN Boot mode. These are the steps that follow:

  1. The device enters the DCAN Boot loader and waits to receive message frames in Mailbox 1. Acceptable messages have a message identifier (MSGID) value of 0x1 for boot-loader communication. For more on mailboxes and MSGID, refer to the DCAN chapter of the device-specific TRM [6].
  2. The flash kernel is transferred to the device with 2 bytes of data per frame. The host programmer will transmit frames to the device, checking if data bytes 3 and 4 are non-zero values. Bytes 3 and 4 of the text file must be replaced with the hex value calculated from the final result of the bit timing register value (CAN_CALC_BTRREG) in order of least significant byte followed by the most significant byte. If the host programmer recognizes a bit-timing change with bytes 3 and 4, the host programmer will then send the bit-timing change to the device and re-initialize itself (skipping the following 7 reserved words). The device will increase the bitrate to the desired bit-timing and continue to receive frames until the kernel has finished download.
  3. The ROM transfers control and the flash kernel begins to execute. There is a small delay in which the kernel must prepare the device for flash programming before it is read to begin communications, and in this time the kernel configures the PLL, flash wait states, and so forth.
    1. The F28P65x and F280015x devices will erase the user-designated flash banks and sectors at this point.
    2. The F28003x kernel erases at a later point
  4. The kernel enters DCAN Boot mode and waits to receive message frames in Mailbox 1. The CAN_CALC_BTRREG value (bootloader_can_timing.h) is adjusted within the project to 1Mbps and the DCAN message buffer size is adjusted by the kernel from 2 bytes per frame to 8 bytes per frame, to allow for a faster download of the application.

  5. The host programmer will delay for 5 seconds before sending the application image at 1 Mbps and payload of 8 bytes per frame.

  6. At the beginning of the download process, a key, a few reserved fields, and the application entry point are read.
    1. The F28003x kernel begins to erase the flash at this point. Erasing flash can take a few seconds, so it is important to note that while it looks like the application load may have failed, it is likely that the flash is just being erased.
  7. Once the flash is erased, the application load continues by transferring frames of data into blocks of application code, and programming that into flash 128-bits or 512-bits at a time.
    1. The F280015x and F28P65x flash kernels program 512-bits at a time
    2. The F28003x flash kernel and 128-bit version of the F28P65x flash kernel program 128-bits at a time
  8. After a block of data is programmed into flash, the kernel continues to receive messages to program the next block of data. This process continues until the entire application has been programmed into flash.

Now that the application is programmed into flash, the flash kernel attempts to run the application by branching to the entry point that was transferred to it at the start of the application load process. A device reset is needed for this.