SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

3.7.1 Hardware Setup and Connections

The following hardware is needed to run the demo:

Optional

  • Logic Analyzer (for viewing TDM bus signals)

Setup the hardware as follows:

  1. Insert the controlCARDs into their corresponding TMDSHSECDOCK. Both controlCARDs should be set to their default settings (see respective user guide for each EVM).
  2. Wire the F28388D output TDM stream to the F280025C input TDM as shown in Table 3-4 and Table 3-5.
    Table 3-4 F280025C CLB Logic Input TDM Signals
    TDM Input Pin GPIO (BALL) DOCK Pin
    FSYNC_IN GPIO00 49
    BCLK_IN GPIO01 51
    DATA1_IN GPIO02 53
    Table 3-5 F28388D McBSP Output TDM Signals
    TDM Input Pin GPIO (BALL) DOCK Pin
    MCLKX/BCLK GPIO22 72
    MFSX/FSYNC GPIO23 74
    MDX/DATA1 GPIO20 68
  3. Wire the F280025C output TDM stream to the F28388D input TDM as shown in Table 3-6 and Table 3-7.
    Table 3-6 F280025C CLB Logic Output TDM Signals
    TDM Output Pin GPIO (BALL) DOCK Pin
    FSYNC_OUT GPIO04 50
    BCLK_OUT GPIO05 52
    DATA1_OUT GPIO06 54
    Table 3-7 F28388D McBSP Input TDM Signals
    TDM Input Pin GPIO (BALL) DOCK Pin
    MCLKR/BCLK GPIO58 108
    MFSR/FSYNC GPIO59 110
    MDR/DATA1 GPIO21 70
  4. Wire a couple of common GND connections between the two docking stations.
  5. Connect the corresponding USB cables to each controlCARD.
  6. Connect the 5V supply to each TMDSHSECDOCK (alternatively use a separate USB cable to power the docking station).
  7. Set S1 to the "EXT_ON" position on each TMDSHSECDOCK.