SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

3.5.3 FSYNC and DATA1 Output Synchronization

The DATA1_OUT signal will always be delayed with respect to the incoming BCLK_IN and FSYNC_IN signals given internal data movement delays in the CLB tile (see Figure 3-10). In order to generate FSYNC_OUT and DATA1_OUT signals that are aligned to each other, two FSMs were used to latch and hold these signals. The output latches are updated on the rising edge of BCLK_IN.

FSM0 is used to detect and delay FSYNC_IN. This means the FSYNC_IN signal is not directly passed through the FSYNC_OUT signal. The state diagram is shown in Figure 3-8 and the corresponding truth table is shown in Table 3-2.

Figure 3-8 FSM0 State Machine for TDM-8 Example
Table 3-2 FSM0 Truth Table for TDM-8 Example
S1 S0 E1
(FSYNC high & BCLK low)		 E0
(BCLK rise)		 S1 Next S0 Next OUT
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 1 0
0 0 1 1 0 0 0
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 0
0 1 1 1 0 0 0
1 0 0 0 1 0 1
1 0 0 1 0 0 1
1 0 1 0 0 0 1
1 0 1 1 0 0 0
1 1 0 0 0 0 0
1 1 0 1 0 0 0
1 1 1 0 0 0 0
1 1 1 1 0 0 0

The reduced logic equations are:

  • S1 (NEXT) = !E1&!E0&S1&!S0 | !E1&E0&!S1&S0
  • S0 (NEXT) = !E1&!E0&!S1&S0 | E1&!E0&!S1&!S0
  • OUT = !E1&S1&!S0 | !E0&S1&!S0

FSM2 is used to implement a simple D-type flip-flop which will latch and delay the DATA1_OUT signal. The truth table is shown in Table 3-3. Notice from Table 3-3 that S0 (next) is used to drive the final DATA1_OUT signal.

Table 3-3 FSM2 Truth Table for TDM-8 Example
E1
(DATA1)		 E0
(BCLK rise)		 S0 S0 (next)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

The reduced logic equation is:

  • S0 (NEXT) = !E0&S0 | E1&E0