SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

4.5.1 TX Tile Logic

The logic for the TX tile is shown in Figure 4-6.

Figure 4-6 CLB TX Tile Logic

The following CLB tile resources are used to implement the CCSI bus transmit (TX) functionality:

  • COUNTER0 is used to count the number of words to transmit. It is operated in normal counter mode.
  • COUNTER1 is used to transmit the output data on SCLKX2 falling edges. It is operated in serializer mode.
  • COUNTER2 is used to count SCLKX2 falling edges. It is operated in normal counter mode.
  • The HLC is used to move data into COUNTER1 from the CLB PULL FIFO. It also generates interrupts to the CPU when four 16-bit words are transmitted and when the full frame has been transmitted.
  • FSM0 is used to cycle through IDLE, ACTIVE, and END states.
  • FSM2 is used to count when four 16-bit words have been transmitted. An event is generated to the HLC when the transmit count reaches four.

Several LUTs and output LUTs are used for combinatorial logic.

FSM0 define three states of operation for the TX tile. The FSM0 state diagram and truth table are shown in Figure 4-7 and Table 4-2.

Figure 4-7 FSM0 State Diagram for TX Tile
Table 4-2 FSM0 Truth Table
S1 S0 E1
(TRANSFER_
START)		 E0
(C0_MATCH1)		 S1 Next S0 Next Output
(FSM0_OUT)
0 0 0 0 0 0 1
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 1 0

0
0 1 1 0 0 1 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 1 0 1
1 0 1 1 1 0 1
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 0 1

The reduced logic equations are:

  • S1 = !S1&S0&E0 | S1&!S0&E1
  • S0 = !S1&E1&!E0 | !S1&S0&!E0
  • OUTPUT = !S0 | S1

FSM2 is used to trigger an HLC event once four 16-bit words have been transmitted. The FSM2 state diagram and truth table are shown in Figure 4-8 and Table 4-3.

Figure 4-8 FSM2 State Diagram for TX Tile
Table 4-3 FSM2 Truth Table
S1 S0 E1
(FSM0_OUT)		 E0
(C2_MATCH1)		 S1 Next S0 Next Output
(HLC_INT)
0 0 0 0 0 0 0
0 0 0 1 0 1 0
0 0 1 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 0
0 1 1 1 0 0 0
1 0 0 0 1 0 0
1 0 0 1 1 1 0
1 0 1 0 0 0 0
1 0 1 1 0 0 0
1 1 0 0 1 1 0
1 1 0 1 0 0 1
1 1 1 0 0 0 0
1 1 1 1 0 0 0

The reduced logic equations are:

  • S1 = S1&!S0&!E1 | S1&!E1&!E0 | !S1&S0&!E1&E0
  • S0 = !S0&!E1&E0 | S0&!E1&!E0
  • OUTPUT = S1&S0&!E1&E0