SPRAD62 February   2023 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Serial Port Design Methodology
    1. 2.1 Step 1: Understand Design Requirements
    2. 2.2 Step 2: Identify Required Inputs to the CLB Tile
      1. 2.2.1 GPIO Input Qualification
      2. 2.2.2 CLB Input Settings
    3. 2.3 Step 3: Identify Required Outputs from CLB Logic
      1. 2.3.1 Synchronizing Outputs Signals
      2. 2.3.2 Output Signal Conditioning
    4. 2.4 Step 4: Design the CLB Logic
      1. 2.4.1 Resource Allocation
      2. 2.4.2 Exchanging Data Between CLB FIFOs and MCU RAM
      3. 2.4.3 CLB Logic Status and Trigger Flags
        1. 2.4.3.1 Status/Flag Bits
        2. 2.4.3.2 Trigger Bits
    5. 2.5 Step 5: Simulate the Logic Design
    6. 2.6 Step 6: Test the CLB Logic
  5. 3Example A: Using the CLB to Input and Output a TDM Stream in Audio Applications
    1. 3.1 Example Overview
    2. 3.2 Step 1: Understand Design Requirements
    3. 3.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 3.4 Step 3: Identify Required Outputs from CLB Logic
    5. 3.5 Step 4: Design the CLB Logic
      1. 3.5.1 Resource Allocation
      2. 3.5.2 TDM Word Counter
      3. 3.5.3 FSYNC and DATA1 Output Synchronization
    6. 3.6 Step 5: Simulate the Logic Design
    7. 3.7 Step 6: Test the CLB Logic
      1. 3.7.1 Hardware Setup and Connections
      2. 3.7.2 Software Setup
      3. 3.7.3 Testing Output Setup and Hold Times
      4. 3.7.4 Testing Data Integrity
  6. 4Example B: Using the CLB to Implement a Custom Communication Bus for LED Driver in Lighting Applications
    1. 4.1 Example Overview
    2. 4.2 Step 1: Understand Design Requirements
    3. 4.3 Step 2: Identify Required Inputs to the CLB Tile
    4. 4.4 Step 3: Identify Required Outputs From CLB Logic
    5. 4.5 Step 4: Design the CLB Logic
      1. 4.5.1 TX Tile Logic
      2. 4.5.2 RX Tile Logic
      3. 4.5.3 Data Clocking
    6. 4.6 Step 5: Simulate the Logic Design
    7. 4.7 Step 6: Test the CLB Logic
      1. 4.7.1 Hardware Setup and Connections
      2. 4.7.2 Software Setup
      3. 4.7.3 Testing Output Setup and Hold Times
  7. 5References

4.3 Step 2: Identify Required Inputs to the CLB Tile

The input signals to the TX tile are shown in Figure 4-3.

Figure 4-3 TX Tile Input Signals

The TX tile use the following inputs:

  • CLB input 0: This input is internally driven by the PWMnA output. The PWMnA output is configured to generate a clock at 2x the target SCLK frequency. The TX tile transmits data using the PWMnA clock.
  • CLB input 3: This input is internally driven by the PWMnA output. The input is passed through the tile and used to drive the CLB_SCLKX2 output.
  • CLB input 4: This input is internally driven by a PWMnB output. The PWMnB output is configured to generate a clock at the target SCLK frequency. The input is passed through the tile and used to drive the CLB_SCLK output.

The TX tile also uses three auxiliary signals for synchronizing data transmission on all TX tiles:

  • CLB input 1: The GPREG.1 bit is used to start a data transfer on the TX tile. It is set/cleared by the CPU.
  • CLB input 5: This input used as an external transfer start signal to the TX tile. This input is always taken from CLB tile 2, output 5.
  • CLB input 6: The GPREG.6 bit drives the external transfer start signal on all TX tiles in cases where more than one TX tile is used. Only GPREG.6 in CLB tile 2 can be used to start transfers in other TX tiles. The GPREG.6 bit is set/cleared by the CPU.

The input signals to the RX tile are shown in Figure 4-4.

Figure 4-4 RX Tile Input Signals

The RX tile uses the following inputs:

  • CLB input 1: This input is used to receive data from the SIN pin.
  • CLB input 2: This input is used to trigger data reception on the falling edge of CLB_SCLKX2. The CLB_SCLKX2 signal is an external clock provided by the TX CLB tile which runs at 2x the frequency of SCLK.
  • CLB input 3: The GPREG.3 bit is used to enable/disable data reception. It is set/cleared by the CPU.