SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

3.5.3.3 Mask Report

The minimum jitter and noise margins are to be captured with respect to the eye mask(s). This masks are data rate dependent, and includes:

  • Data read eye mask at the SOC die pad for functionality testing
  • Data write eye mask (JEDEC spec) at the DRAM pin/BGA for compliance testing
  • CA bus eye mask (JEDEC spec) at the DRAM pin/BGA for compliance testing

There should be at least 2 sets of eye diagrams generated by the simulator:

  • Vref set to the optimal Vref of the byte offset by the Vref_set_tol in the positive direction (Vref_set_tol is defined in JEDEC spec)
  • Vref set to the optimal Vref of the byte offset by the Vref_set_tol in the negative direction

The system-level margins are the worst case noise and jitter margins from all eye diagram measurements listed above (across SSHT and FFLT corners). For all waveforms captured at the DRAM device, margins should be calculated at both the BGA pin and the DRAM pad.

Table 3-3 LPDDR4 Eye Mask Definitions/Requirements
Parameter Mask Shape LPDDR4-3200 LPDDR4-3733
CA eye mask TclVW Rectangular (1) 0.3 UI (1) (2)
CA eye mask VclVW Rectangular (1) 155 mV (1) (2)
Write eye mask TdlVW Rectangular (1) 0.25 UI (1) (2)
Write eye mask VdlVW Rectangular (1) 140 mV (1) (2)
Read eye mask TdlVW Diamond 0.61 UI 0.66 UI
Read eye mask VdlVW Diamond 140 mV 140 mV
(1) Copied from JEDEC specification: Low Power Double Date Rate 4 (LPDDR4).
(2) For details, contact the DRAM vendor.

Figure 3-4 through Figure 3-6 show the eye mask definitions translated to eye diagrams within captured waveforms.

GUID-6435A4B2-931F-4F8A-9510-1AA88CB4E674-low.png Figure 3-4 Example Simulated LPDDR4-4266 Read Eye With Diamond-Shaped Eye Mask
GUID-4DB31CCD-12DC-4F6B-BCD0-39B73098E90B-low.png Figure 3-5 Example Simulated LPDDR4-4266 Write Eye With Rectangular JEDEC Eye Mask
GUID-A8047071-2859-46AC-9260-E67292289CC8-low.png Figure 3-6 Example Simulated LPDDR4-4266 CA Eye With Rectangular JEDEC Eye Mask