SPRAD66B February 2023 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1
The examples below from a J7 design show the LPDDR4 Clock and CA routing on an example 10-layer PCB design. The clock is routed differentially with target impedance of 70Ω. For the T-branch to match the impedance of the trace, the impedance needs to be doubled. This can create challenges, as the higher impedances can be difficult to achieve in some PCB stackups. The CA signals are routed targeting 35Ω, with the T-branch at two times the source impedance.
On the same 10 layer reference design, the data groups are routed on layers 2 and 4. The upper layers are used due to the minimum via travel, which minimized the via inductance and via-to-via coupling. Because the data signals are point-to-point, T-branch routing is not required.
Routing Layer | Via Type | Back Drilling | EW Margin (ps) | EH Margin (mV) |
---|---|---|---|---|
L1, L12 | PTH | No | -7.10 | 56.72 |
L1, L12 | PTH | Yes | -4.86 | 55.71 |
L1, L3 | PTH | No | 5.70 | 40.29 |
L1, L3 | PTH | Yes | 8.37 | 34.54 |
Routing Layer | Via Type | Back Drilling | EW Margin (ps) | EH Margin (mV) |
---|---|---|---|---|
L1, L12 | PTH | No | 17.42 | 39.22 |
L1, L12 | PTH | Yes | 20.04 | 41.93 |
L1, L3 | PTH | No | 27.66 | 41.37 |
L1, L3 | PTH | Yes | 27.76 | 48.63 |