SPRAD66B February   2023  – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Additional Information: SOC Package Delays
  8. 5Summary
  9. 6References
  10. 7Revision History

2.7 Net Classes

Routing rules are applied to signals in groups called net classes. Each net class contains signals with the same routing requirements. This simplifies the implementation and compliance of these routes. Table 2-4 lists the clock net classes for the LPDDR4 interface. Table 2-5 lists the signal net classes, and associated clock net classes, for signals in the LPDDR4 interface. These net classes are then linked to the termination and routing rules that follow.

Table 2-4 Clock Net Class Definitions
Clock Net ClassProcessor Pin Names
CK0DDR0_CK0 / DDR0_CK0_n
DQS0DDR0_DQS0 / DDR0_DQS0_n
DQS1DDR0_DQS1 / DDR0_DQS1_n
DQS2DDR0_DQS2 / DDR0_DQS2_n
DQS3DDR0_DQS3 / DDR0_DQS3_n
Table 2-5 Signal Net Class Definitions
Signal Net ClassAssociated Clock Net ClassProcessor Pin Names
ADDR_CTRLCK0DDR0_A[5:0], DDR0_CS0_n, DDR0_CS1_n, DDR0_CKE0, DDR0_CKE1, DDR0_CAS_n(1), DDR0_RAS_n(1)
BYTE0DQS0DDR0_DQ[7:0], DDR0_DM0
BYTE1DQS1DDR0_DQ[15:8], DDR0_DM1
BYTE2DQS2DDR0_DQ[23:16], DDR0_DM2
BYTE3DQS3DDR0_DQ[31:24], DDR0_DM3
(1) When used with LPDDR4, the DDR0_CAS_n and DDR0_RAS_n pins output copies of the chip selects to support point to point connections to Channel B chip selects on the LPDDR4 device. DDR0_CAS_n = copy of CS1 for LPDDR4_CS1_B, DDR0_RAS_n = copy of CS0 for LPDDR4_CS0_B