SPRAD66B February 2023 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1
The required interconnect delays for DQ, DQS, CA, and CLK are listed in Section 2.13 and Section 2.14. The values listed as Typical are only recommendations. Any minimum or maximum value is a requirement. One key requirement is to make sure the CK delay is greater than any DQS delay. DQSx delays must also be less than the DQ and DM delays in the respective BYTEx. Consider the complete system from SOC die pad, through the PCB, to the pins of the memory package.