1 Introduction

Dual clock comparator (DCC) is primarily intended to determine the clock accuracy during the application execution. The exact accuracy is programmable and should be calculated for each application. It can also be used to determine the frequency of any selectable clock, using another independent input clock as a reference. It uses two independent clock sources to detect when one is out of spec.

Clock frequency drift is inevitable, which can occur due to multiple reasons such as environmental conditions like humidity, pressure and temperature, aging, and so forth. Impact of aging can be noticed when the device has been on the field for a few years, and the clocks start drifting causing catastrophic implications if not monitored. Hence, DCC is particularly useful in safety critical automotive/ industrial timing applications.

DCC contains three counters – counter0 (20-bit), valid0 (16-bit) and counter1 (20-bit). Initially, all counters are loaded with their user-defined, pre-load value. Counter0 and counter1 start decrementing once the DCC is enabled at rates determined by the frequencies of clock0 and clock1, respectively. When counter0 equals 0 (expires), the valid0 counter decrements at a rate determined by clock0. If counter1 decrements to 0 in the valid window, then no error is generated and clock1 is considered to be good within allowable tolerance as configured by the user. An error is generated when the frequency is not within the allowable tolerance, and counter1 doesn't decrement within the valid window (either when clock0 /clock1 is absent or clock1 expired before the counter0 reaches 0 or clock1 expired after both counter0 and valid0 reach 0).

Counter0 and counter1 are configured based on the ratio between the frequencies of clock0 and clock1 (Fclk1×Counter0 = Fclk0×Counter1). The valid0 counter provides tolerance and is configured based on the allowed frequency error and the inherent DCC error (asynchronous and digitization error). Since clock0 and clock1 are asynchronous, the start and stop of the counters do not occur synchronously. Hence, while configuring the counters, two different sources of errors must be accounted for, which are:

• DCC Error due to the asynchronous timing of clock0 and clock1 - This depends on the frequency of clock0 and clock1:
  • If Fclk1 > Fclk0, then Async. Error (In Clock0 cycles) = 2 + 2×(Fsysclk/Fclk0)
  • If Fclk1 < Fclk0, then Async. Error (In Clock0 cycles) = 2×(Fclk0/Fclk1) + 2×(Fsysclk/Fclk0)
  • If Fclk1 is unknown, then Async. Error (In Clock0 cycles) = 2 + 2×(Fsysclk/Fclk0) Note: Fsysclk is 200MHz
• Digitization error - 8 Clock0 cycles

The following formulas are used by the tool to compute the counter0, valid0 and counter1 seed values:

• Counter0 Seed = Window - Total Error
• Valid0 Seed = 2 × Total Error
• Counter1 Seed = Window × (Fclk1/Fclk0)

Where,

• DCC Error (in Clock0 Cycles) = Async. Error + 8 Clock0 Cycles (Digitization error)
• Minimum accuracy possible (%) = (100 × DCC Error × (Fclk1/Fclk0)) / 1048575
• Window (in Clock0 Cycles) = (DCC Error) / (0.01×Minimum accuracy possible (in %))
• Frequency Error Allowed (In Clock0 Cycles) = Window × (Minimum accuracy possible (in %) / 100)
• Total Error (in Clock0 Cycles) = DCC Error + Frequency Error Allowed

The DCC computation tool provides the register values to be programmed in-order to compare any given system or peripheral clock against a configurable reference clock to determine if the frequency of the said clock is within the expected accuracy. The accuracy required can be provided as an input, and the tool calculates the counter seed values based on that. There is a separate calculator present for each of the four instances: DCC0, DCC1, DCC2 and DCC3.