SPRAD85B September 2024 – December 2024 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1
DDR Subsystem currently supports LPDDR4 memory interface. Refer Memory Subsystem, DDR Subsystem (DDRSS) section in the Features chapter of device-specific data sheet for data bus width, inline ECC support, speed and max addressable range selection.
The allowed memory configurations are 1 x 32-bit or 1 x 16-bit.
1 x 8-bit memory configuration is not a valid configuration.
Based on the application requirements, same memory (LPDDR4) device can be used with the AM625 / AM623 / AM625-Q1 / AM620-Q1 , AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 , AM62D-Q1 and AM62P / AM62P-Q1 processor families due to the availability of 1 x 16-bit configuration.
When the AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1 processors are configured for 16-bit configuration, follow the DQS2-3 and other unused signal connection recommendations shown in the 16-Bit, Single Rank LPDDR4 Implementation example of the AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines.
Refer Pin Connectivity Requirements section of the device-specific data sheet for connecting the DDRSS signals when not used.
For more details, refer the DDR Subsystem (DDRSS) section in the Memory Controllers chapter of the device-specific TRM.
For more information on DDR4 / LPDDR4 memory interface, see the [FAQ] AM625 / AM623 / AM62A / AM62P Design Recommendations / Commonly Observed Errors during Custom board hardware design – DDR4 / LPDDR4 MEMORY Interface. The FAQ is generic and can also be used for AM62D-Q1 processor family.