SPRAD89 March   2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Use-case Considerations
  5. 3Interfacing the High Voltage Sensor
    1. 3.1 Consideration for Proper ADC Sampling
    2. 3.2 Handling High Impedance Sensor
  6. 4Performance Considerations
    1. 4.1 ADC Gain, Offset, INL & DNL
    2. 4.2 SNR Consideration
    3. 4.3 Performance Advantage
  7. 5Conclusion
  8. 6References

4.1 ADC Gain, Offset, INL & DNL

Assume the ADC has an offset m LSB. Now assume V1 is the input voltage and LSB is the step size of the actual 3.3 V SAR ADC inside Sitara MCU (≈3.3/2^12). The ADC generates an output code ‘c’ with input of ‘V1’ and has an offset of ‘m’ LSB.

Equation 3. V 1   =   c   ×   L S M   +   m   ×   L S B    
Equation 4. c   =   ( V 1 / L S B )   +   m

Now assume V2 is applied at the input of the Resistor ladder, so at the input of ADC the voltage

Equation 5. V 3   =   V 2   ×   R 1 / ( R 1   + R 2 )
Equation 6. C 2   =   ( V 3 / L S B )   +   m
Equation 7. V 3   =   C 2   ×   L S B   +   m   ×   L S B
Equation 8. V 2   =   C 2   ×   L S B   × ( R 1   +   R 2 ) / R 1   +   m   ×   L S B   ×   ( R 1   +   R 2 ) / R 1

Comparing the previous two equations, one can say the resistor ladder simply scales the LSB size and the offset effectively remains the ‘same number of LSBs’ as it was with the 3.3 V ADC. The gain error and INL, DNL also can be proven to be scaled in same way.

In simple words if the 3.3 V ADC has an offset error of 2 LSB (with LSB=3.3/4096), then at the input of the resistor ladder it still has a 2 LSB offset error with a slightly larger LSB=5/4096.