The thermal via array implementation is arguably the most important aspect of thermal design for the AM263x since unless there is a heatsink used for the BGA package, the thermal vias are the only heat-sinking thermal connection for the BGA package. The thermal vias for the AM263x are in the form of the ground return vias attached to each VSS pin of the BGA.

The thermal resistance of thermal vias (RΘ_vias) relates to the total thermal resistance of all thermal vias beneath the SoC. Each individual thermal via is analogous to a resistor where the equivalent resistance of all resistors is similar to many parallel resistors. Similar to an increasing number of parallel resistors and equivalent resistance, there are diminishing returns on the equivalent thermal resistance with each additional thermal via. For example, in a case where a single via has a thermal resistance of 50℃/Watt then Figure 3-1 shows the relationship between number of thermal vias and the equivalent thermal resistance (assuming that all vias have the exact same properties).

The dimensions of a thermal via are what determine a single thermal via's thermal resistance. a general rule of thumb is that RΘ_vias is estimated by the following equation:

$\frac{\frac{1}{\lambda \left(Cu\right)}\left(Length\right)}{Area}=R\Theta Single Via$

Where λ(Cu) is the conductivity of copper or 4 Watts per meter-kelvin, length refers to the length of the via, and the equation for thermal via area is:

$\pi *{\left[\right(Drill Hole Radius)}^2-{(Drill Hole Radius - plating thickness)}^2]$

Figure 3-2 shows an example of the thermal via array with 8mil holes and 10 mil trace width from the BGA to the thermal vias.

For best thermal performance:

• Use vias on each VSS pin of the BGA
• Use widest possible traces from the BGA to the via
• Use the largest possible drill diameter
• Conductively fill the thermal vias