SPRADC1 june   2023 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Different Types of Memories on the TDA4VM
  5. 2Memory Overview and Intended Usage
    1. 2.1 PSROM
      1. 2.1.1 Typical Use Cases
    2. 2.2 PSRAM
      1. 2.2.1 Typical Use Cases
    3. 2.3 MSMC RAM
      1. 2.3.1 Typical Use Cases
      2. 2.3.2 Relevant Links
    4. 2.4 MSRAM
      1. 2.4.1 Typical Use Cases
    5. 2.5 ARM Cortex A72 Subsystem
      1. 2.5.1 L1/L2 Cache Memory
      2. 2.5.2 L3 Memory
      3. 2.5.3 Relevant Links
    6. 2.6 ARM Cortex R5F Subsystem
      1. 2.6.1 L1 Memory System
      2. 2.6.2 Cache
      3. 2.6.3 Tightly Coupled Memory (TCM)
      4. 2.6.4 Typical Use Case
      5. 2.6.5 Relevant Links
    7. 2.7 TI's C6x Subsystem
      1. 2.7.1 Memory Layout
      2. 2.7.2 Relevant Links
    8. 2.8 TI's C7x Subsystem
      1. 2.8.1 Memory Layout
      2. 2.8.2 Relevant Links
    9. 2.9 DDR Subsystem
      1. 2.9.1 Relevant Links
  6. 3Performance numbers
    1. 3.1 SDK Data Sheet
    2. 3.2 Memory Access Latency
  7. 4Software Careabouts When Using Different Memories
    1. 4.1 How to Modify Memory Map for RTOS Firmwares
    2. 4.2 DDR Sharing Between RTOS Core and HLOS
    3. 4.3 MCU On-Chip RAM Usage by Bootloader
    4. 4.4 MSMC RAM Default SDK Usage
      1. 4.4.1 MSMC RAM Reserved Sections
      2. 4.4.2 MSMC RAM Configuration as Cache and SRAM
    5. 4.5 Usage of ATCM from MCU R5F
    6. 4.6 Usage of DDR to Execute Code from R5F
  8. 5Summary

3.2 Memory Access Latency

Table 3-1 and Table 3-2 illustrate the relative memory access latency (read) from each core to primary memory end-points in the SoC system. Table 3-1 shows the latency for a core to access different memory end-points with access to DDR as a baseline. For example, in the first row of Table 3-1, the A72 core has a latency to access MSMC that is 33% of the latency to access DDR. Latencies to MCU OCRAM and MAIN OCRAM are both greater than the latency to DDR. Table 3-2 compares the latency from each core to DDR, with the A72 core’s access to DDR as the baseline. The MCU R5 core takes 2.55x longer to access DDR than the A72 core.

It should be noted that DDR access latency is typically not constant due to factors such as SDRAM refresh cycles and periodic retraining. To provide an accurate comparison, this analysis uses optimal DDR access latency by excluding non-deterministic factors. Other SRAM-based memory end-points do not have variance in access latency.

Overall, these tables provide insight into the relative memory access latency for each core in the system, with implications for system performance and optimizations.

Note that the relative performance in Table 3-2 is for the worst case latency, such that, in cases when the data is read from the physical memory rather than the cache. If data being processed has a lot of locality, then the caches will hide most of the latency. The performance boost of using the different memories starts to show up as the cache miss rate increases. Observed performance from a source to a destination can vary depending on caching and contention. The SDK data sheet compares the cached performance using benchmarks like LMBench for Linux running on A72 and a memory benchmarking application for FreeRTOS running on R5F.

Table 3-1 Relative Latency From Each Core to Memory End-Point
DDR MSMC C7x L2SRAM C6x L2SRAM MCU OCRAM MAIN OCRAM
A72 1.00x 0.33x 0.38x 1.30x 1.59x 1.13x
C7x 1.00y 0.36y 0.03y 1.24y 1.50y 1.08y
C6x 1.00z 0.63z 0.67z 0.01z 0.52z 0.28z
MCU R5F 1.00a 0.73a 0.78a 0.54a 0.20a 0.47a

MAIN R5F

 1.00b 0.71b 0.75b 0.51b 0.53b 0.42b
Table 3-2 Comparison of DDR Access Latency From Each Core
A72 C7x C6x MCU R5F MAIN R5F
DDR 1.00c 1.12c 1.98c 2.55c 2.37c

From above tables, items which should be considered during system design:

  • Using memory local to the processor where software is running, results in reduced memory access latency, when compared to DDR
  • When using memory to share data between cores (A72/R5/C6/C7)
    • The memory access time will be different depending on the core the software is running on.
    • Care should be taken when selecting which memory will be used to share the data
  • MSMC memory, has low access time from all cores, when compared to DDR. Use of MSMC memory can lead to increased performance in many use cases. The most efficient use of this memory for the overall system should be reviewed.