SPRADC3 june   2023 AM2431 , AM2432 , AM2434 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to 8b-10b Line Coding
  5. 2PRU Implementation for Data Transmitting and Receiving
    1. 2.1 Encoding and Decoding Data
    2. 2.2 PRU Module Interface and GPIO Mode
    3. 2.3 PRU GPIO Shift-out and Shift-in Mode for Communication
    4. 2.4 Three-channel Peripheral Interface for Communication
    5. 2.5 LVDS and M-LVDS Interface
  6. 3System Solution With CRC Module and Over-head Optimization
    1. 3.1 PRU CRC16/32 Module
    2. 3.2 Encode and Decode Over-head Optimization
  7. 4Verification
  8. 5Summary
  9. 6References

2.4 Three-channel Peripheral Interface for Communication

The 3-channel peripheral interface can also support data transmission that is similar to the GPIO shift mode. Since this application note is focused on the GPIO shift mode, the 3-channel peripheral interface is only briefly introduced in this section. The detailed introduction of 3-channel peripheral mode can be found in the AM62x Processors Silicon Revision 1.0 Texas Instruments Families of Products technical reference manual.

The PRU uses the R30 and R31 registers to interface with the peripheral interface (I/F). The transmit (TX) First in First out (FIFO) buffer is 32-bits and can operate with continuous mode while receiving a (RX) FIFO buffer size of 4 bits with maximum eight times oversampling. Both the TX and RX clock can be sourced either by ICSS_UART_CLK or ICSS_CORE_CLK. There are two independent clock dividers for TX and RX clock and each clock divider is configurable by two cascading dividers. Figure 2-9 shows the block diagram of a single-channel peripheral I/F where the other 2 channels are the same.

GUID-20230614-SS0I-TWPT-0JLH-LGGJ1DVZPSRS-low.svg Figure 2-9 Single-channel Peripheral I/F Block Diagram

The basic programming model for Three Peripheral Mode can be found in the AM62x Processors Silicon Revision 1.0 Texas Instruments Families of Products technical reference manual.