SPRADC3 june   2023 AM2431 , AM2432 , AM2434 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3358-EP , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM5749 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to 8b-10b Line Coding
  5. 2PRU Implementation for Data Transmitting and Receiving
    1. 2.1 Encoding and Decoding Data
    2. 2.2 PRU Module Interface and GPIO Mode
    3. 2.3 PRU GPIO Shift-out and Shift-in Mode for Communication
    4. 2.4 Three-channel Peripheral Interface for Communication
    5. 2.5 LVDS and M-LVDS Interface
  6. 3System Solution With CRC Module and Over-head Optimization
    1. 3.1 PRU CRC16/32 Module
    2. 3.2 Encode and Decode Over-head Optimization
  7. 4Verification
  8. 5Summary
  9. 6References

3.2 Encode and Decode Over-head Optimization

As the 8b-10b encoding method described in preceding sections describes, the 8-bit data generates 10-bit encoded data and is stored in 2 bytes of the REG_ENC register which leaves 6 bits unused in byte 2. The transmitting buffer is a 16-bit width so that the data can be combined and transmitted continuously to reduce the over-head. Figure 3-3 shows the optimized approach for transmitting encoded data:

GUID-20230614-SS0I-JW7Z-J2LN-SQBNDSSPPHQC-low.svg Figure 3-3 Optimized Approach for Transmitting Encoded Data

One transmitting cycle pattern is 80-bits encoded data width (64-bits original data width) with 8 times encoding process.

Similar to the approach for transmitting encoded data, Figure 3-4 shows the optimized process for receiving decoded data:

GUID-20230614-SS0I-DPMQ-RSJK-73VVW4T1SCWV-low.svg Figure 3-4 Optimized Approach for Receiving Decoded Data

One receiving cycle pattern is 80-bits decoded data width with 8 times decoding process.

The original frame pattern can be a 64-bit width with 16-bit preamble, 32-bit data words, and 16-bit CRC data. To increase the efficiency, RTU_PRU0 and RTU_PRU1 auxiliary cores can be used for encoding, decoding, and CRC16 workloading in parallel. Figure 3-5 shows a block diagram with both PRU and RTU cores.

GUID-20230606-SS0I-QGFP-WLGK-H1ZMPMFHJQ7D-low.svg Figure 3-5 System Block Diagram With PRU and RTU Cores