SPRADD2 august   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 AM62A Processor
  6. 3 System Block Diagram
  7. 4 Driver and Occupancy Mirror System Data Flow
  8. 5 Deep Learning Acceleration
  9. 6 Functional Safety in DMS/OMS Applications Using AM62A
    1. 6.1 Overview of Functional Safety Features on AM62A
  10. 7 Functional Safety Targets and Assumptions of Use
  11. 8 Functional Safety in DMS/OMS Data Flow
  12. 9 LED Driver Illumination Use Case
  13. 10Summary
  14. 11References

2 AM62A Processor

The AM62A microprocessor is a heterogeneous processor designed for camera analytics applications. There are different hardware accelerators optimized for different tasks thus enabling an optimized power and cost footprint. TI’s image signal processor called the Vision processing accelerators (VPAC), Quad Arm® Cortex®-A53 cores along with TI proprietary C7x DSP and matrix multiplication accelerator (MMA) make the AM62A Sitara™ MPU, well suited for vision-based applications such as driver and occupancy monitoring and associated eye safety.

Functional safety compliance on AM62Ax is another differentiating factor which enables OEMs and Tier1s to target safety functions on auto or industrial systems integrated with AM62A. With this device, system integrators can target safety use cases such as monitoring the driver for sleep/alertness, child presence detection as well as comfort functions such as driver identification, HMI interaction, in-vehicle video calls, and so forth. AM62Ax device is targeting safety compliance to ISO-26262 ASIL-B and IEC-61508 SIL-2 for random fault integrity as well as ASIL-D / SIL-3 for systematic capability. Various on-chip diagnostics, freedom from interference features along with embedded MCU domain for safety monitoring reduces overall BOM cost by enabling application processing as well as safety functions on the same device.

GUID-20230807-SS0I-7NR3-XHFM-N6RP7V1VMJ7X-low.svg Figure 2-1 AM62A Simplified Block Diagram

The main processing and compute subsystems from a camera mirror system context in AM62A are as follows:

  • Quad Arm Cortex-A53 cores: These can run up to 1.4 GHz and provide up to 16.8k Dhrystone Million Instructions Per Second (DMIPS) of performance.
  • C7 Digital Signal Processor (DSP) and Matrix Multiplication Accelerator (MMA): TI’s deep learning accelerator on AM62A is capable of two TOPs operations when clocked at 1GHz.
  • Vision Processing Accelerator (VPAC3L): The latest generation in TI ISP technology for performing image operations some examples of which are color conversions, chromatic aberration correction, pyramid scaling and lens distortion correction. It also has dedicated hardware support for 4x4 RGB-IR color filter arrays (CFA) – a must for next generation DMS/OMS systems. VPAC3L has a total throughput of up to 300MP/s.
  • VPU: The video processing unit has support for H.264/H.265 encode/decode with up to a total throughput capability of 240MP/s.