SPRADD2 august   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. AM62A Processor
  6. System Block Diagram
  7. Driver and Occupancy Mirror System Data Flow
  8. Deep Learning Acceleration
  9. Functional Safety in DMS/OMS Applications Using AM62A
    1. 6.1 Overview of Functional Safety Features on AM62A
  10. Functional Safety Targets and Assumptions of Use
  11. Functional Safety in DMS/OMS Data Flow
  12. LED Driver Illumination Use Case
  13. 10Summary
  14. 11References

Overview of Functional Safety Features on AM62A

GUID-20230807-SS0I-NZ3B-TSLV-5KKN8ZV0XQ0R-low.svg Figure 6-1 Overview of AM62A Functional Safety Features

Similar to several other Sitara MPU family of functional safety compliant devices, AM62A offers a myriad of safety features to meet targeted safety integrity levels for automotive and industrial applications. Key features are highlighted below.

  • Device infrastructure enables partitioning the device into MCU domain for safety intensive functions and Main domain for application processing alone or a mix of application processing and safety functions. Safety infrastructure includes firewall isolation, ECC/parity on MCU domain interconnect and I/O safe mode.
  • Safety diagnostics tool kit includes dedicated IP that facilitate safety monitoring, detection and reporting. Examples of such IP are DCC – Dual Clock Comparators, Internal Watchdogs, ECC aggregators, MCRC – Memory CRC, ESM – Error Signal Monitoring, VTM – Temperature Monitors, POK – Undervoltage and Overvoltage monitors, and so forth. Such dedicated diagnostic logic along with internal interrupt routing enable detection and reporting of faults within reasonable FTTI.
  • Self-test capability includes memory BIST capability on several memories and LBIST capability on MCU domain core. Test for diagnostic features such as ECC/parity are also available on the device.
  • Safe compute features such as memory protection units (MPU) and memory management units enable memory protection for cores. Software mechanisms such as program sequence monitoring, reciprocal comparison by software etc. are recommended in the safety manual for the detection of faults in CPU execution.
  • Freedom from interference is provided by firewalls, timeout gaskets, clock gating features and hardware support for independent reset of main domain.
  • Several hardware and software diagnostics can be enabled at a per functional IP level so as to meet application specific needs. For example, MISR data integrity checks in VPAC and DSS, hardware provided CSI protocol checks, and so forth.
  • Common cause failure detection and reporting is enabled via dual clock comparators, on-chip clock loss detection logic, and so forth.