SPRADD9 September   2023 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Optimized ePWM Configurations
    1. 1.1 Cycle by Cycle (CBC) Protection
    2. 1.2 Reverse Current Control
    3. 1.3 ePWM Configurations Proposed
  5. 2How to Better Use the CMPSS for Totem Pole PFC
  6. 3How to Control the Slow Frequency MOSFETs
  7. 4How to Implement Reliable Zero-Crossing Detection
  8. 5How to Implement 2 Phase Interleaved Control
  9. 6References

How to Implement Reliable Zero-Crossing Detection

As discussed in How to reduce current spikes at AC zero-crossing for totem-pole PFC, it is critical to implement the soft-start scheme for Q1~Q4 during the zero-crossing point to reduce the current spike and improve THD. Before that, accurate and reliable AC voltage zero-crossing detection is most important. In the reference designs, Design Guide: TIDM-2008/TIDM-1007 - Bidirectional Interleaved CCM Totem Pole Bridgeless PFC Reference Design Using C2000™ MCU or Design Guide: TIDA-010203 - 4-kW, Single-Phase Totem Pole PFC Reference DesignWith C2000 and GaN, software phase-locked loop (SPLL) is leveraged to detect the zero-crossing point with the voltage phase information. As a low-pass filter, SPLL is a good method to avoid the error caused by the sensing voltage noise or spike. However, if the actual applications need to support the step change of the AC frequency, SPLL could not provide the expected performance due to the calculation delay. Thus, it is still necessary to understand how to achieve accurate zero-crossing detection with the pure voltage sensing circuits using ADC.

GUID-20230825-SS0I-RN7K-X6RM-DMH362WTZX67-low.svg Figure 4-1 CMPSS Used for Vac Sensing

As shown in Figure 4-1, CMPSSx is suggested to enable for the Vac sensing signal, with the DAC threshold set closed to 0. With the help of the CMPSS, it is possible to shut down all the switches controlled by ePWM modules as soon as the AC polarity changes without any software delay. During the normal operation, it can naturally provide the dead time before the zero-crossing point when the soft-start scheme starts to implement, as discussed in How to reduce current spikes at AC zero-crossing for totem-pole PFC.

In the actual applications, the rectifier diodes are also added to bypass surge current. The most critical issue during the surge test is that, for example during the positive cycle, when the reverse surge energy forces the AC voltage polarity from positive to negative for a short time, the AC source will be in short circuits since Q4 keeps the on state as in the positive cycle, as shown in Figure 4-2. Thus, with the CMPSSx enabled for Vac sensing, it will turn off Q4 so as to avoid the short circuit condition within 55ns, which minimizes the risk of the damage to the power stage. During the normal conditions, turning off the switches when the AC voltage goes through the threshold voltage during the zero-crossing point is also unexpected. In addition, it is also helpful when testing with non-sinusoidal AC voltage input, even with square wave type AC input.

GUID-20230825-SS0I-6GLQ-Z3FB-CG3Q645JDQH9-low.svg Figure 4-2 Short Circuit Issue During the Surge Test