SPRADG0A April   2024  – August 2024 AM62P , AM62P-Q1

 

  1.   Abstract
  2.   2
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Change Cortex-A53 Clock Frequency
  5. 2Processor Core and Compute Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 CoreMark-Pro
    3. 2.3 Fast Fourier Transform
    4. 2.4 Cryptographic Benchmarks
    5. 2.5 IPC Mailbox Latency
  6. 3Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
    2. 3.2 Critical Memory Access Latency
    3. 3.3 UDMA: DDR to DDR Data Copy
  7. 4Graphics Processing Unit Benchmarks
    1. 4.1 Glmark2
    2. 4.2 GFXBench5
  8. 5Video Codec
  9. 6References
  10. 7Revision History

3.2 Critical Memory Access Latency

This section provides round-trip read latency measurements for processors in AM62Px to various memory destinations in the system. The measurements where made on the AM62Px platform using bare-metal silicon verification tests. The tests execute on A53 and R5F processor out of LPDDR4. Each test includes a loop of 8192 iterations to read a total of 32 KiB of data. The number of cycles for each access were counted and divided by the respective processor clock frequency to obtain latency time. Table 3-4 shows the average latency results.

Table 3-4 Critical Memory Access Latency of A53, R5F MCU, and R5F WKUP
MemoryArm-Cortex-A53
(Avg ns)		Arm-Cortex-R5F MCU
(Avg ns)		Arm-Cortex-R5F WKUP
(Avg ns)
LPDDR4129207173
OCSRAM MAIN5612076
OCSRAM MCU12055

80

OCSRAM WKUP207193153
R5F MCU TCM1401180
R5F WKUP TCM1041111

Tests were done at 0.75V VDD_CORE, 1.25Ghz A53 cores, 800MHz R5F cores, and 3200MT/s LPDDR4. Tightly-Coupled Memory, or TCM, is RAM that is directly attached to an ARM Cortex core. ARM architecture provides a local internal low latency path and also allows external access to the memory through SoC bus infrastructure.