The AM62Px device contains a Mailbox IP as one of the primary methods of inter-processor communication (IPC). The Mailbox module serves to facilitate the communication between the various on-chip processors of the device by providing a queued mailbox-interrupt mechanism.

The queued mailbox-interrupt mechanism allows the software to establish communication channels between multiple processors (users) through a set of registers and associated interrupt signals with a small 32-bit payload.⁽¹⁾ The Mailbox consists of 8 groups of FIFOs (clusters) that support bidirectional communication between a maximum of 4 users.

Each cluster contains a series of 16 FIFOs, each supporting unidirectional communication between up to 4 users. Each FIFO holds up to 4 32-bit messages.

The measurements were made on the AM62Px platform using bare-metal silicon verification tests. The R5F cores operated out of local TCM, while A53 cores operated out of DDR. Each test included a loop of 32 send/receive iterations, whose results were averaged. Two methods of servicing received messages were used: one using processor interrupts (shown in Table 2-6), and the other using polling (shown in Table 2-7).