During benchmarking on AM62x, one Common Platform Switch (CPSW) ethernet interface is connected the EtherCAT network and the other CPSW ethernet interface is connected to the PC running CODESYS Development System to view EtherCAT statistics. Due to how CPSW is designed with 2 external ports connected to a single internal port, all frames passing through the 2 external ports pass through the single internal port. This design prevents the possibility of distinctly isolating any ethernet related interrupts between the two external ports. As a result, isolating which CPU core the packets pass through is not possible. The only potential method to control which CPU core the packets get processed is through application level threads. If one application only uses one external port and the other application uses another, set the cpu affinity of each application to the desired CPU core. However, this setup still does not mean that the ethernet interrupts use the desired CPU core. Another reason for why the two external ports cannot be distinct, from an interrupt and CPU core perspective, is because both CPSW ports are using the same CPSW ethernet driver. Isolating the two external ports by using CPSW for one and Industrial Control Communication Subsystem - Gigabit (ICSSG) ethernet for the other port is possible as this strategy can use two separate ethernet drivers.