SPRADH0 August   2024 AM625 , AM6442 , AM69 , TDA4VM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 What is EtherCAT?
    2. 1.2 What is a PLC?
    3. 1.3 What is CODESYS?
  5. 2Evaluation Platform and Methods
    1. 2.1 Hardware
    2. 2.2 Software
    3. 2.3 Test Topology
  6. 3Performance Metrics
    1. 3.1 Cyclictest Performance Metrics
    2. 3.2 EtherCAT Performance Metrics
  7. 4Optimizations
    1. 4.1 Implemented Optimizations
    2. 4.2 Future Considerations
      1. 4.2.1 Set Maximum CPU Frequency
      2. 4.2.2 Isolate Cores
      3. 4.2.3 Set CPU Affinity
      4. 4.2.4 Isolate Cores and Set CPU Affinity
      5. 4.2.5 Ksoftirqs to FIFO
      6. 4.2.6 Increase the Real-Time Scheduling Time
      7. 4.2.7 Disable irqbalance
      8. 4.2.8 Use Separate Network Interface Card (NIC)
      9. 4.2.9 Disable Unnecessary Drivers
  8. 5Summary
  9. 6References
  10. 7Appendix A: How to Setup TI Embedded Processors as EtherCAT Controller Using the CODESYS Stack
    1. 7.1 Hardware Requirements
    2. 7.2 Software Requirements
    3. 7.3 Hardware Setup
    4. 7.4 Software Setup
      1. 7.4.1 Windows PC Setup
      2. 7.4.2 EtherCAT Controller Setup
      3. 7.4.3 CODESYS Development System Project
      4. 7.4.4 Execution
    5. 7.5 How to View Performance Measurements
      1. 7.5.1 Appendix A Resources
  11. 8Appendix B: How to Enable Unlimited Runtime on CODESYS Stack
    1. 8.1 CODESYS Licensing Background
    2. 8.2 Obtaining a CODESYS License
    3. 8.3 Activating CODESYS License
      1. 8.3.1 Background
      2. 8.3.2 Recommended Steps
    4. 8.4 Verifying CODESYS License Applied
      1. 8.4.1 Known Issues With Verifying CODESYS License Applied

3.1 Cyclictest Performance Metrics

Before evaluating the performance of each hardware platform when running an EtherCAT application, gathering baseline performance statistics from running cyclictest is typically recommended. These statistics are a good indicator to the performance of an EtherCAT controller when running the CODESYS stack.

cyclictest is a utility tool in Linux (see also, the Linux Foundation) that accurately and repeatedly measures the difference between the intended wake-up time of a thread and the time at which the thread actually wakes up to provide statistics about the latencies of the system. Latencies caused by hardware, firmware, and the operating system in real-time systems can be measured by cyclictest.

The results of cyclictest are plotted in the same histogram format as the data Open Source Automation Development Lab (OSADL) publishes in QA Farm on Real-time of Mainline Linux. OSADL is an organization intended to facilitate individuals, groups, and companies to develop Open Source software by bringing in a broader community to help with development. A service provided by OSADL is the QA farm, which is a quality assurance and assessment test center for embedded systems.

The results of cyclictest were captured on the AM62x evaluation board (SK-AM62B), AM64x evaluation board (TMDS64EVM), TDA4VM starter kit (SK-TDA4VM), and AM69 starter kit (SK-AM69) to show the base latencies running on these platforms. SK-AM62B and TMDS64EVM ran on PROCESSOR-SDK-LINUX-RT-AM62x and PROCESSOR-SDK-LINUX-RT-AM64x default wic image, respectively, from Software Development Kit (SDK) version 09.01.00.08. The TDA4VM and AM69 ran on real-time builds from the respective SDK 09.01.00.06 versions. Each cyclictest ran for 6 hours under stress test using the stress-ng tool. See the following code snippet for this setup.

stress-ng -c <number of cpu cores> --cpu-method all &
cyclictest -m -Sp98 -D6h -h400 -i200 -q > <histogram name>.hist
AM6442, AM625, AM69 Latency Plot for AM62x Running for 6 Hours Under stress-ngFigure 3-1 Latency Plot for AM62x Running for 6 Hours Under stress-ng
AM6442, AM625, AM69 Latency Plot for AM64x Running for 6 Hours Under stress-ngFigure 3-2 Latency Plot for AM64x Running for 6 Hours Under stress-ng
AM6442, AM625, AM69 Latency Plot for AM69 Running for 6 Hours Under stress-ngFigure 3-3 Latency Plot for AM69 Running for 6 Hours Under stress-ng
AM6442, AM625, AM69 Latency Plot for the TDA4VM Running for 6 Hours Under stress-ngFigure 3-4 Latency Plot for the TDA4VM Running for 6 Hours Under stress-ng