SPRADH0 August   2024 AM625 , AM6442 , AM69 , TDA4VM

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 What is EtherCAT?
    2. 1.2 What is a PLC?
    3. 1.3 What is CODESYS?
  5. 2Evaluation Platform and Methods
    1. 2.1 Hardware
    2. 2.2 Software
    3. 2.3 Test Topology
  6. 3Performance Metrics
    1. 3.1 Cyclictest Performance Metrics
    2. 3.2 EtherCAT Performance Metrics
  7. 4Optimizations
    1. 4.1 Implemented Optimizations
    2. 4.2 Future Considerations
      1. 4.2.1 Set Maximum CPU Frequency
      2. 4.2.2 Isolate Cores
      3. 4.2.3 Set CPU Affinity
      4. 4.2.4 Isolate Cores and Set CPU Affinity
      5. 4.2.5 Ksoftirqs to FIFO
      6. 4.2.6 Increase the Real-Time Scheduling Time
      7. 4.2.7 Disable irqbalance
      8. 4.2.8 Use Separate Network Interface Card (NIC)
      9. 4.2.9 Disable Unnecessary Drivers
  8. 5Summary
  9. 6References
  10. 7Appendix A: How to Setup TI Embedded Processors as EtherCAT Controller Using the CODESYS Stack
    1. 7.1 Hardware Requirements
    2. 7.2 Software Requirements
    3. 7.3 Hardware Setup
    4. 7.4 Software Setup
      1. 7.4.1 Windows PC Setup
      2. 7.4.2 EtherCAT Controller Setup
      3. 7.4.3 CODESYS Development System Project
      4. 7.4.4 Execution
    5. 7.5 How to View Performance Measurements
      1. 7.5.1 Appendix A Resources
  11. 8Appendix B: How to Enable Unlimited Runtime on CODESYS Stack
    1. 8.1 CODESYS Licensing Background
    2. 8.2 Obtaining a CODESYS License
    3. 8.3 Activating CODESYS License
      1. 8.3.1 Background
      2. 8.3.2 Recommended Steps
    4. 8.4 Verifying CODESYS License Applied
      1. 8.4.1 Known Issues With Verifying CODESYS License Applied

4.2 Future Considerations

There are several additional steps to gain better visibility into why the CODESYS EtherCAT stack is affecting the CPU load and KPI as described in the previous section. These steps have not yet been extensively investigated but are described here as potential future steps to take. Many of these steps are based on suggestions given on the CODESYS Optimization for Linux Systems resource.

The optimizations described in the previous section are predominately discovered through experimentation. What is currently known is that when the CODESYS application is started on each hardware platform, a list of several threads related to the application appear. Figure 4-9 shows an example of this observation using an htop capture. This htop is taken during the time the Codemeter application caused a spike in CPU load. CODESYS documentation refers to these threads as “IEC tasks”.

The thread with priority -56 is specifically the EtherCAT task scheduled with a FIFO priority scheme. This can be verified by checking on the CODESYS Development System and the associated priority found on the CODESYS Mapping of Task Priorities on a Linux System resource. Understanding the function of the other CODESYS threads (“IEC tasks”) is more difficult.

AM6442, AM625, AM69 CODESYS Related Threads on AM62xFigure 4-9 CODESYS Related Threads on AM62x

To gain more visibility, the following steps can be taken:

  • Enable kernel tracing (ftrace) to detect if an interrupt or another service can be interfering with the performance of the EtherCAT task

  • Implement CPU load tracing object in CODESYS Development System for better granularity of CPU load over time

  • Run cyclictest while CODESYS EtherCAT application is running in the background to see if the metrics significantly differ from cyclictest running with stress-ng. The motivation for doing this task is to see if the metrics match up with EtherCAT cycle time and to see if the maximum latencies increased in a that is way indicative of large amounts of ethernet traffic.

Other experiments to try include the following. Keep in mind that for each experiment, first testing the results using cyclictest can be beneficial compared to the more extensive process of capturing data from CODESYS.