SPRADH9
June 2024
AM6442
1
Abstract
Trademarks
1
Abbreviations
2
Introduction
2.1
Peripheral Component Interconnect Express
2.1.1
Components of PCIe Communication
2.1.1.1
Root Complex
2.1.1.2
Repeater
2.1.1.3
Endpoints
2.1.2
Signaling
2.1.2.1
PERST
2.1.2.2
WAKE and CLKREQ
2.1.2.3
REFCLK
2.1.3
PCIe Common Usage
2.1.4
PCIe Aggregate Throughput
2.2
PCIe Features on AM64x and AM243x
3
X86 as RC and AM64x as EP
3.1
Hardware Environment
3.2
Software Environment
3.2.1
Building Application
3.2.2
Usage
4
Test Setup
4.1
Common Setup for LINUX and WIN
4.2
Linux Driver (VFIO)
4.2.1
Prerequisites
4.2.2
Building
4.2.3
Deploying
4.3
Test Application Usage
4.4
Setup Steps for LINUX PC
4.4.1
UART Console Output
4.5
MSI Example
4.6
Setup Steps for WINDOWS PC
4.6.1
Prerequisites
4.6.2
Building
4.6.3
Deploying
5
PCIe Test Specification
5.1
Identification and Configuration Functionalities
5.1.1
Test Case
5.2
Reference Clock Functionalities
5.3
Inbound ATU and BAR Functionalities
5.4
Outbound ATU Functionalities
5.5
MSI Functionality
5.6
Downstream Interrupt Functionality
5.7
Device Power Management State Functionality
5.8
Function Level Reset Mechanism
5.9
Legacy Interrupt Mechanism
5.10
MSI-X Capability
5.11
Hot Reset Mechanism
6
Windows Example Driver Verification
7
References
1
Abbreviations
PCIe
Peripheral Component Interconnect Express
PCI-SIG
PCI Special Interest Group
EP
End Point
RC
Root Complex
SSC
Spread Spectrum
BIOS
Basic Input Output Software
CCS
Code Composer Studio
TI
Texas Instruments
BAR
Base Address Register
MSI
Message Signal Interrupt
MSI-X
Message Signal Interrupt X
SBL
Secondary Bootloader
VFIO
Virtual Function I/O
IOMMU
I/O Memory Management Unit
ATU
Address Translation Unit
FLR
Function Level Reset