The backbone of the design process is defined under the umbrella of Process Delivery Kit (PDK) for the technology node. From a reliability perspective, once the silicon wafer manufacturing process baseline flow is defined, component-level reliability is executed by the wafer fab. These tests assess potential intrinsic wear-out mechanisms that can effectively limit the useful lifetime of the final product. Generally, the tests are highly-accelerated, meaning stress conditions are much more aggressive than final product application use conditions, and are tested to failure to enable characterization of reliability models (which can involve testing a multiple stress conditions to define acceleration models.) Each test has defined pass/fail criteria, consistent with the overall reliability targets of the silicon technology. Critically, the component-level tests can be performed at much higher levels of stress than HTOL testing, enabling granular reliability models (necessitating observed failures) and compressed execution times.