Soft start process is aimed to build up the output voltage with controlled slew rate, which can avoid current inrush on both primary side and output side for LLC. Figure 4-1 summarizes the soft start flow.

In the first stage of soft start, it requires to turn on the low side FET to charge the bootstrap capacitor, since the half bridge uses bootstrap power supply for the high side gate driver. This charging pulse can be much longer than driver’s turn on delay, and make sure the bootstrap capacitor is completely charged.

As discussed in the Section 3.3, since the low side PWM (EPWM1B) is generated by the high side PWM (EPWM1A), EPWM1B can’t be set to high independently. To generate the bootstrap pulse to EPWM1B, but keeping EPWM1A low, the CLB for PWML included another input to handle the bootstrap logic. As shown in Figure 3-4, the CLB input with GPREG bit (Input 4) is leveraged to create the AND logic with FSM0_S0 for EPWM1B, so that changing GPREG bit to logic “0” can set high for EPWM1B regardless of EPWM1A status. Users can define the timing for the on-time of EPWM1B based on system requirements, while keeping EPWM1A low with a large rising edge delay in the DB module configured.

In the second stage, the resonant capacitor voltage needs to be biased to the half of the input voltage, since for half bridge LLC, the offset of VCR is excluded in the HHC control algorithm. This bias voltage can be built up by several symmetry pulses of both the high side and the low side switches. The symmetrical pulses can be generated by a large compensating slope, which turns the HHC into traditional frequency adjusting as voltage mode control.

Then, in the third stage, the output voltage is built up with close loop control and gradually increase the voltage reference from 0V to 12V. When the reference is slewed up to the targeted setting voltage, the soft start process completes. The control scheme during this stage is explained in detail in the later section.

The fourth stage is the beginning of the normal operation. Note that SR PWM output is disabled to avoid any unexpected reverse current during the soft start process, and the initial slope compensation is enlarged to maintain stability control. In this stage, the SR PWM output can be slowly turned on by gradually reducing the deadtime of EPWM to the minimum setting value. In addition, both the slope and the minimum frequency clamping values are gradually recovered in this stage.

There are five control parameters can be adjusted in the HHC control algorithm, shown in Figure 4-2.

1. Control band, Vci
2. Deadtime of primary EPWM, Td
3. Compensating slope, slope
4. Minimum frequency clamping, fmin
5. Maximum frequency clamping, fmax

During the soft start process, deadtime adjustment is included to reduce the inrush current when the output voltage is not high enough. And the mixed control of deadtime and control band adjustment is shown in Figure 4-2. When the voltage loop’s compensator output Vc_v is higher than 0, the deadtime Td is set to the minimum value, and the control band Vci is increased from the minimum boundary. When Vc_v is lower than 0, Vci is set to the minimum value, and Td is increased from the minimum setting. Besides, if actual applications require to clamp the minimum on-time for the PWM pulse, it is possible to set the maximum deadtime limitation to achieve this feature. It means that if the deadtime calculated is larger than the maximum one, PWM output is directly turned off, so as to enter burst mode control naturally.

And during the third stage, the compensating slope is temporarily increased to a larger value to avoid oscillation and keep the control loop stable. The slope is reduced by 1unit once Vci reaches the maximum limitation, and can be gradually reduced to the targeted value after the soft start.

In addition, at the beginning of the soft start, the minimum switching frequency clamping fmin is temporarily increased higher than the resonant frequency, which is used to avoid entering the capacitive region when the output voltage is not high enough. And, the maximum frequency is also temporarily increased, to get lower voltage gain. Both minimum and maximum frequency clamping are gradually reduced to the normal value during or after the soft start process.