CLB is a peripheral on C2000 MCUs consisting of a number of look-up tables (LUTs), finite-state machines (FSMs) and counters which can be configured to perform complex logic operations. The LUT submodule can be used to implement simple combinatorial logic such as inverting a signal or ANDing multiple signals together. The FSM submodule can be used to implement state-based logic, such as an SR latch. The counter submodule features a 32-bit count register and can be used to perform operations such as counting the number of cycles a signal is high as well as dividing a clock signal. Interconnecting these submodules together can enable countless functions in a variety of applications. Each CLB tile contains a high-level controller (HLC) which can be triggered by signals within the CLB to perform set instructions. These instructions can include adding registers, subtracting registers, moving data between registers in the CLB, signaling interrupts to the CPU, and sending and receiving data from the CPU.

In the HHC LLC design, 2 CLB tiles are required. As for the synchronous rectification (SR) control, the challenge is to define the on time for SR PWM using normal EPWM configurations in advance, since the comparator event decides the turn-off timing of the primary-side PWM. Thus, CLB is leveraged to simplify the SR control for HHC LLC. For more details, please refer to Hardware-Based Synchronous Rectification Control with CLB.

For the primary side PWM configurations, CLB is used to make sure the identical pulse width of the high side and low side PWM signals (EPWM1A and EPWM1B). As shown in Figure 3-3, CLB is used to generated the AQ module output signal for EPWM1B, based on EPWM1A’s AQ module output signal. EPWM1A’s AQ module output signal is used to control the counter direction of CLB counter, which can start to count down after EPWM1A clears low. The natural way is to generate the symmetry counter signal. Then, by leveraging the falling edge of EPWM1A and the counter = 0 events, the expected signal for the EPWM1B can be generated by FSM.

As indicated in Table 3-1, it is possible to use FSM0_S0 to override the AQ module output of EPWM1B, by assigning FSM0_S0 to Output 5 of the CLB1 module, directly with the CLB multiplexer output enable register CLB_OUT_EN.

Note that to add the rising edge delay to the EPWM1B final output signal, the FSM output generated by CLB is inverted first, then the falling edge delay can be enabled within the DB module.

In addition, the requirement is to generate the synchronization event for EPWM1 module at the falling edge of EPWM1B, which can be achieved by routing FSM_S0 output to the CLB output (Output 4), and then through EPWM X-BAR to configure the synchronization scheme.

A completed CLB configuration block diagram is shown in Figure 3-4.