SPRADN4 December   2024 AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Application Note Usage Guidelines
      1. 1.1.1 Processor Family Specific Application Note
      2. 1.1.2 Schematics Design Guidelines
      3. 1.1.3 Schematic Review Checklist
      4. 1.1.4 FAQ Reference for Application Note Usage Guidelines
    2. 1.2 AM62P Processor Family
      1. 1.2.1 AM62P
      2. 1.2.2 AM62P-Q1
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
    2. 2.2 Hardware Design Considerations for Custom Board
  6. 3 Processor Selection
    1. 3.1 Data Sheet Use Case and Version References in the Application Note
    2. 3.2 Device Selection and OPN
    3. 3.3 Peripheral Instance Naming Convention
    4. 3.4 Unused Peripherals
    5. 3.5 Processor Ordering and Quality
    6. 3.6 Processor Selection Checklist
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM62P and AM62P-Q1
        1. 4.1.1.1 PMIC
          1. 4.1.1.1.1 PMIC Checklist
          2. 4.1.1.1.2 Additional References
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
          3. 4.1.1.2.3 Discrete Power Checklist
    2. 4.2 Power Control and Circuit Protection
      1. 4.2.1 Load Switch (Power Switching)
        1. 4.2.1.1 Load Switch Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
      1. 5.1.1 Evaluation Module Checklist
    2. 5.2 Device-Specific (Processor-Specific, Processor-Family Specific) SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistors
        7. 5.2.1.7 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding Reuse of SK Design
        1. 5.2.2.1 Updated SK Schematic With Design, Review and CAD Notes Added
          1. 5.2.2.1.1 AM62P / AM62P-Q1
        2. 5.2.2.2 SK Design Files Reuse
          1. 5.2.2.2.1 Reuse of SK Design Checklist
    3. 5.3 Before Beginning the Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison and IOSET
      4. 5.3.4  RSVD Reserved Pins (Signals)
      5. 5.3.5  Note on PADCONFIG Registers
      6. 5.3.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.3.7  Reference to Device-Specific SK
      8. 5.3.8  High-Speed Interface Design Guidelines
      9. 5.3.9  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      10. 5.3.10 Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      11. 5.3.11 Queries and Clarifications Related to Processor During Custom Board Design
      12. 5.3.12 Before Beginning the Design Checklist
      13. 5.3.13 Device Recommendations
  9. 6 Processor-Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 AM62P, AM62P-Q1
          2. 6.1.1.1.2 Additional Information
          3. 6.1.1.1.3 Processor Core and Peripheral Core Power Supply Checklist
          4. 6.1.1.1.4 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 AM62P, AM62P-Q1
          2. 6.1.1.2.2 Additional Information
          3. 6.1.1.2.3 Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 VPP Checklist
        4. 6.1.1.4 Supply Connection for Partial IO Mode (Low-Power) Configuration
          1. 6.1.1.4.1 Partial IO Used
          2. 6.1.1.4.2 Partial IO Unused
          3. 6.1.1.4.3 Data Sheet Reference for Power Sequence
          4. 6.1.1.4.4 Partial IO Low Mode Checklist
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62P / AM62P-Q1
        2. 6.1.2.2 Additional Information
          1. 6.1.2.2.1 AM62P / AM62P-Q1
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI / MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI / WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
          5. 6.1.3.1.5 Clock Input Checklist - MCU_OSC0
          6. 6.1.3.1.6 Clock Input Checklist - WKUP_LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG and EMU Used
      2. 6.2.2 JTAG and EMU Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Groups
      1. 7.1.1 AM62P / AM62P-Q1
      2. 7.1.2 Supply Connections for IO Groups Checklist
    2. 7.2 Memory Interface (DDRSS (DDR4 / LPDDR4), MMCSD (eMMC / SD / SDIO), OSPI / QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM62P / AM62P-Q1
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM62P / AM62P-Q1
            1. 7.2.1.2.1.1 Memory Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
            6. 7.2.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM62P / AM62P-Q1
            1. 7.2.2.1.1.1 MMC0 Used
              1. 7.2.2.1.1.1.1 IO Power Supply
              2. 7.2.2.1.1.1.2 eMMC (Attached Device) Reset
              3. 7.2.2.1.1.1.3 Signals Connection
              4. 7.2.2.1.1.1.4 Capacitors for the Power Supply Rails
            2. 7.2.2.1.1.2 MMC0 Not Used
            3. 7.2.2.1.1.3 MMC0 (eMMC) Checklist
          2. 7.2.2.1.2 Additional Information on eMMC PHY
          3. 7.2.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.2.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.2.3 Signals Connection
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
          6. 7.2.2.2.6 MMC1 SD Card Interface Checklist
        3. 7.2.2.3 MMC1 / MMC2 SDIO (Embedded) Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 Signals Connection
          3. 7.2.2.3.3 MMC2 SDIO (Embedded) Interface Checklist
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI / QSPI Reset
        3. 7.2.3.3 Signals Connection
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
        7. 7.2.3.7 OSPI / QSPI Implementation Checklist
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Connection
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
        6. 7.2.4.6 GPMC Interface Checklist
    3. 7.3 External Communication Interface (Ethernet (CPSW3G), USB2.0, UART and Controller Area Network (CAN))
      1. 7.3.1 Ethernet Interface Using CPSW3G (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Ethernet PHY Reset
        3. 7.3.1.3  Ethernet PHY Pin Strapping
        4. 7.3.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5  MAC (Data, Control and Clock) Interface Signals Connection
        6. 7.3.1.6  External Interrupt (EXTINTn)
          1. 7.3.1.6.1 External Interrupt (EXTINTn) Checklist
        7. 7.3.1.7  MAC (Media Access Controller) to MAC Interface
        8. 7.3.1.8  MDIO (Management Data Input/Output) Interface
        9. 7.3.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
        10. 7.3.1.10 Capacitors for the Power Supply Rails
        11. 7.3.1.11 Ethernet Interface Checklist
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (n = 0-1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C®
        2. 7.3.2.2 USBn (n = 0-1) Not Used
        3. 7.3.2.3 Additional Information
        4. 7.3.2.4 USB Interface Checklist
      3. 7.3.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.3.3.1 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.3.4 Controller Area Network (CAN)
        1. 7.3.4.1 Controller Area Network Checklist
    4. 7.4 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
        1. 7.4.1.1 MCSPI Checklist
        2. 7.4.1.2 MCASP Checklist
      2. 7.4.2 Inter-Integrated Circuit (I2C)
        1. 7.4.2.1 I2C Interface Open-drain Output Type Buffer Checklist
        2. 7.4.2.2 I2C Interface Emulated Open-drain Output Type Buffer Checklist
    5. 7.5 User Interface (CSIRX0, DPI, OLDI0, DSI), GPIO and Hardware Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
        3. 7.5.1.3 CSIRX0 Checklist
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 Display Parallel Interface (DPI)
          1. 7.5.2.1.1 AM62P / AM62P-Q1
            1. 7.5.2.1.1.1 IO Power Supply
            2. 7.5.2.1.1.2 DPI (Attached Device) Reset
            3. 7.5.2.1.1.3 Connection
            4. 7.5.2.1.1.4 Signals Connection
            5. 7.5.2.1.1.5 Capacitors for the Power Supply Rails
            6. 7.5.2.1.1.6 DPI (VOUT0) Checklist
        2. 7.5.2.2 Open LVDS Display Interface (OLDI)
          1. 7.5.2.2.1 AM62P / AM62P-Q1
            1. 7.5.2.2.1.1 OLDI0 Used
              1. 7.5.2.2.1.1.1 IO Power Supply
              2. 7.5.2.2.1.1.2 OLDI (Attached Device) Reset
              3. 7.5.2.2.1.1.3 OLDI Interface Compatibility
              4. 7.5.2.2.1.1.4 Capacitors for the Power Supply Rails
              5. 7.5.2.2.1.1.5 OLDI0 Checklist
            2. 7.5.2.2.1.2 OLDI0 Not Used
            3. 7.5.2.2.1.3 Additional Information
        3. 7.5.2.3 Display Serial Interface (DSI)
          1. 7.5.2.3.1 AM62P / AM62P-Q1
            1. 7.5.2.3.1.1 DSITX0 Used
              1. 7.5.2.3.1.1.1 DSITX0 Checklist
            2. 7.5.2.3.1.2 DSITX0 Not Used
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 Availability of CLKOUT on Processor GPIO
        2. 7.5.3.2 Connection and External Buffering
        3. 7.5.3.3 Additional Information
        4. 7.5.3.4 GPIO Checklist
      4. 7.5.4 On-board Hardware Diagnostics
        1. 7.5.4.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.5.4.1.1 Voltage Monitor Pins Used
            1. 7.5.4.1.1.1 Voltage Monitor Checklist
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Internal Temperature Monitoring
          1. 7.5.4.2.1 Internal Temperature Monitoring Checklist
        3. 7.5.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.5.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Processor Pin Configuration Using PinMux Tool
      2. 7.6.2 Schematics Configurations
      3. 7.6.3 Connecting Supply Rails to Pullups
      4. 7.6.4 Peripheral (Subsystem) Clock Outputs
      5. 7.6.5 General Board Bring-up and Debug
        1. 7.6.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.6.5.2 Additional Information
        3. 7.6.5.3 General Board Bring-up and Debug Checklist
  11. 8 Layout Notes (Added on the Schematic)
    1. 8.1 Layout Checklist
  12. 9 Custom Board Design Simulation
  13. 10Additional References
    1. 10.1 FAQ Covering AM6xx Processor Family
    2. 10.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 10.3 Processor Attached Devices
  14. 11Summary
  15. 12References
    1. 12.1 AM625, AM623, AM625SIP, AM625-Q1, AM620-Q1
    2. 12.2 AM62A7, AM62A3, AM62A7-Q1, AM62A3-Q1
    3. 12.3 AM62P / AM62P-Q1
    4. 12.4 Common for all Processor Families
    5. 12.5 Master List of Available FAQs - Processor Family Wise
    6. 12.6 Master List of Available FAQs - Sitara Processor Families
    7. 12.7 FAQs Including Software Related
    8. 12.8 FAQs for Attached Devices
  16. 13Terminology
7.2.2.2.6 MMC1 SD Card Interface Checklist

General

Review and verify the following for the custom schematic design:

  1. The sections above, including relevant application notes and FAQ links.
  2. Pin attributes, signal description, and electrical specifications.
  3. Electrical characteristics, timing parameters and any additional available information.
  4. Include a series resistor (0Ω) on MMC1_CLK placed as close to processor clock output pin as possible to dampen reflections. MMC1_CLK is looped back internally on read transactions, and the resistor can be needed to eliminates possible signal reflections, which can cause false clock transitions. Use 0Ω initially and adjust as required to match the PCB trace impedance.
  5. The MMC1 CLK, CMD, and DAT0..3 signal functions are implemented with SDIO buffers on pins powered from VDDSHV5 (power source that changes the operating voltage from 3.3V to 1.8V as the transfer speed increases).
  6. The MMC1 SDCD and SDWP signal functions are implemented with LVCMOS buffers on pins powered from VDDSHV0, which operate at fixed 1.8V or 3.3V.
  7. The SDIO buffers are designed to support dynamic voltage change. Dynamic voltage scaling is necessary since UHS-I SD cards begins operating with 3.3V signaling and changes to 1.8V signaling when the SD card transitions to one of the higher speed data transfer modes.Processor IO buffers are off during reset. An external pullup is required for any of the processor or attached device IOs that can float. Pullups are needed on all data and command signals. Verify internal pullups are not configured when (improves noise immunity) external pullups are used.
  8. To meet the SD card specification, a 47kΩ pullup is recommended when internal pulls are unexpectedly enabled. The 47kΩ pullup verifies the resulting pull resistance is within the specified range.
  9. When UHS-I speed support is required, implementing an LDO supply that switches between 3.3V and 1.8V is required. Switching IO supply can be an external discrete implementation or internal to the PMIC. Connect the switchable voltage output to the IO supply group, referencing the SD interface signals (VDDSHV5).
  10. When UHS-I speed support is required, while the IO voltage for SD card interface is either 1.8V or 3.3V, the SD card VDD supply is connected to a fixed 3.3V source.
  11. When UHS-I speed support is required, the 3.3V SD card is required to switch through a load switch to allow resetting of the SD card IO supply to 3.3V. Provision to enable the SD card load switch during reset is required.
  12. Provide provision to reset the load switch using the SD card load switch EN signal during cold reset, warm reset and normal operation using processor IO is required to be provided. An option is a 3-input ANDing logic.
  13. During boot, the ROM code checks the status of the card detect pin (SDCD, pin P23). The signal is expected as low to indicate card is detected.

Schematic Review

Follow the list below for the custom schematic design:

  1. Required bulk and decoupling capacitors are provided. Compare with the SK schematics.
  2. Pull values used for the data, command and clock signals. Compare with the relevant SK.
  3. Series resistor value and placement on the clock output signal near to the processor.
  4. When UHS-I speed support is required, verify the IO supply rail switching and the SD card power switching circuits are added.
  5. Supply rail connected to the SD card power supply (use SYS voltage).
  6. Implementation of reset logic for resetting the SD card power control load switch. Provision for slew rate control of the SD card supply is provided.
  7. Supply rails connected follow the ROC.
  8. Required external ESD protection are provided for the SD interface signals.

Additional

  1. The logic state of the MMC1_SDCD and MMC1_SDWP inputs to the host must not change when a UHS-I SD card changes the IO operating voltage. Maintaining a valid logic state is not possible if the signals propagate through an input buffer of a dual-voltage SDIO cell that changes voltage. The signal functions are assigned to IOs that do not change voltage. Signals only connect to switches in the SD card connector, so there is no reason for the signals to change voltage when the SD card signals change operating voltage. The MMC1_SDCD and MMC1_SDWP signals are required to connect to the SD card connector switches and pull high with external pull resistors connected to the VDDSHV0. The other MMC1 SD card signals with pullups are required to have pulls powered by the VDDSHV5 source that dynamically changes voltage.
  2. The MMC2_SDCD and MMC2_SDWP pins are referenced to the same IO supply group the other MMC2 pins. However, the recommendation is not to use the control for the MMC2_SDCD and MMC2_SDWP signal functions if users are trying to connect an UHS-I SD card to MMC2. For SD card use case, the signal functions needs to be implemented using one of the other pin multiplexing options that uses an IO cell powered from a fixed voltage source. The MMC2 assignments are different because we only expected MMC2 to be used with on-board fixed voltage SDIO devices similar to Wi-Fi or Bluetooth® transceivers.
  3. An SD card power switch, the power switch supply EN pin reset logic, and the host IO power supply circuit are required to support UHS-I SD cards, which begins communications using 3.3V signal levels and later changes to 1.8V signal levels when changing to one of the faster data transfer speeds.

    Cycling power to the SD card is the only way to put the SD card back into 3.3V mode since SD cards do not have a reset pin. The host IO power supply must power off and on, and change voltage at the same time as the SD card. The circuits and the software driver operating the signals sourcing the circuits verifies that both devices are off, or on and operating at the same IO voltage at the same time.

  4. To optimize the ANDing logic, use a 2 input AND gate with RESETSTATz and the processor IO as inputs.
  5. Add a series resistor 100Ω to the SDCD pin because the processor IO connects directly to the ground when the SD card is inserted.