For optimizing the design, the processor clock output (CLKOUT0) can be used as clock input to the EPHY. Clock output is buffered internally and is intended to used for a point-to-point clock topology. A series resistor is recommended at the source side of the CLKOUT0 to minimize reflections.

RGMII EPHYs require a 25MHz clock input that is not synchronous to any other signals. 25MHz clock signal does not have any timing requirements, but is important the EPHY does not receive any non-monotonic transitions on the clock input.

RMII EPHY clocking option changes with the EPHY controller or device configuration.

When configured as controller, most RMII EPHYs require a 25MHz input clock that is not synchronous to other signals. The 25MHz clock signal does not have any timing requirements relative the processor, but is important that the EPHY does not receive any non-monotonic transitions on the clock input.

The RMII EPHY provides the 50MHz clock output to the MAC. For RMII use case, the 50MHz data transfer clock is delayed to the MAC relative to the EPHY. The delay shifts clock to data timing relationship which can erode the timing margin. Eroded timing margin can be problematic for some designs if the delay is too large.

When configured as device, the MAC and the EPHY uses a 50MHz common clock that is synchronous to both transmit and receive data. The 50MHz clock is defined in the RMII specification as a common data transfer clock signal that is used by both the MAC and the EPHY, where transitions are expected to arrive simultaneously at the MAC and EPHY device pins. The common clock provides better timing margin for both transmit and receive data transfers. Important requirement is that the MAC and EPHY do not receive any non-monotonic transitions on the clock inputs. To take care of the clock signal integrity, recommendation is to route the common clock signal through a two-output phase aligned buffer. Recommend using equal length signal traces that are half the length of the data signals for connecting the clock buffer outputs, where one clock output connects to the MAC and the other connects to the EPHY.

For RMII interface, the recommended configuration is RMII Interface Typical Application (External Clock Source) explained in the device-specific TRM. If RMII Interface Typical Application (Internal Clock Source) configuration explained in the device-specific TRM is used, the performance has to be validated on a board level. Provision for an external clock for initial performance testing and comparison is recommended. The Ethernet performance (RGMII) is validated on the processor and the EPHY with 25MHz clock.

The CLKOUT0 function can be used to source a 25MHz or a 50MHz clock input to EPHY. However, using CLKOUT0 signal function requires the software to configure the clock output. The CLKOUT0 clock configuration cannot be used if the board design must support Ethernet boot. CLKOUT0 connected as EPHY clock is likely to glitch anytime the configuration is changed.

AM62Ax and AM62Dx processor families, automatically begins sourcing the device reference clock (MCU_OSC0_XO, enabled during reset) to the WKUP_CLKOUT0 pin as soon as the device is released from reset (MCU_PORz 0 to 1). The clock output does not glitch after the clock begins to toggle. However, the first high or low pulse can be short because reset is released asynchronous to the HFOSC0 clock.

The EPHYs are required to be held in reset for a specified minimum reset hold time after the respective clocks are valid.

Processor clock output performance is not defined because clock performance is influenced by many variables unique to each custom board design. The board designer must validate timing of all peripherals by using the actual PCB delays, minimum or maximum output delay characteristics, and minimum setup and hold requirements of each device to confirm there is enough timing margin.