SPRADO2B November   2024  – January 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Application Note Usage Guidelines
      1. 1.1.1 Custom Board Design - Implementation References
      2. 1.1.2 Processor Family Specific Application Note
      3. 1.1.3 Schematic Design Guidelines
      4. 1.1.4 Schematic Review Checklist
      5. 1.1.5 FAQ Reference for Application Note Usage Guidelines
    2. 1.2 Family Wise List of Processors
      1. 1.2.1 AM62Ax Processor Family
      2. 1.2.2 AM62Dx Processor Family
  5. 2 Related Collaterals
    1. 2.1 Links to Commonly Available and Applicable Collaterals
      1. 2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
      2. 2.1.2 AM62D-Q1
    2. 2.2 Hardware Design Considerations for Custom Board Design
  6. 3 Processor Selection
    1. 3.1 Data Sheet Use Case and Version Referenced
    2. 3.2 Processor Selection (OPN Orderable Part Number)
    3. 3.3 Peripheral Instance Naming Convention
    4. 3.4 Unused Peripherals
    5. 3.5 Processor Ordering and Quality
    6. 3.6 Processor Selection Checklist
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
        1. 4.1.1.1 Power Management IC (PMIC)
          1. 4.1.1.1.1 PMIC Checklist for TPS6593x
          2. 4.1.1.1.2 PMIC Checklist for TPS65224x
          3. 4.1.1.1.3 Additional References
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
          3. 4.1.1.2.3 Discrete Power Checklist
    2. 4.2 Power Control and Circuit Protection
      1. 4.2.1 Load Switch (Power Switching)
        1. 4.2.1.1 Load Switch Checklist
      2. 4.2.2 eFuse IC (Power Switching and Protection)
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (SK - Starter Kit)
      1. 5.1.1 Evaluation Module Checklist
    2. 5.2 Processor-Specific SK Versus Data Sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Resistor
        2. 5.2.1.2 Parallel Pull Resistor
        3. 5.2.1.3 Drive Strength Configuration
        4. 5.2.1.4 Data Sheet Recommendations
        5. 5.2.1.5 Processor IOs - External ESD Protection
        6. 5.2.1.6 Peripheral Clock Output Series Resistor
        7. 5.2.1.7 Component Selection Checklist
      2. 5.2.2 Additional Information Regarding Reuse of SK Design
        1. 5.2.2.1 Updated SK Schematic With Design, Review and CAD Notes Added
        2. 5.2.2.2 SK Design Files Reuse
          1. 5.2.2.2.1 Reuse of SK Design Checklist
    3. 5.3 Before Beginning the Design
      1. 5.3.1  Documentation
      2. 5.3.2  Processor Pin Attributes (Pinout) Verification
      3. 5.3.3  Device Comparison, IOSET and Voltage Conflict
      4. 5.3.4  RSVD Reserved Pins (Signals)
      5. 5.3.5  Note on PADCONFIG Registers
      6. 5.3.6  Processor IO (Signal) Isolation for Fail-Safe Operation
      7. 5.3.7  Reference to Processor-Specific SK
      8. 5.3.8  High-Speed Interface Design Guidelines
      9. 5.3.9  Recommended Current Source or Sink for LVCMOS (GPIO) Outputs
      10. 5.3.10 Connection of Slow Ramp Inputs or Capacitors to LVCMOS IOs (Inputs or Outputs)
      11. 5.3.11 Queries and Clarifications Related to Processor During Custom Board Design
      12. 5.3.12 Before Beginning the Design Checklist
      13. 5.3.13 Device Recommendations
  9. 6 Processor-Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supply for Core and Peripherals
          1. 6.1.1.1.1 Power Supply Ramp (Slew Rate) Requirement and Dynamic Voltage Scaling / Change
          2. 6.1.1.1.2 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
          3. 6.1.1.1.3 Additional Information
          4. 6.1.1.1.4 Processor Core and Peripheral Core Power Supply Checklist
          5. 6.1.1.1.5 Peripheral Analog Power Supply Checklist
        2. 6.1.1.2 Supply for IO Groups
          1. 6.1.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
          2. 6.1.1.2.2 Additional Information
          3. 6.1.1.2.3 Supply for IO Groups Checklist
        3. 6.1.1.3 Supply for VPP (eFuse ROM Programming)
          1. 6.1.1.3.1 VPP Checklist
        4. 6.1.1.4 Supply Connection for Partial IO (Low-Power) Mode Configuration
          1. 6.1.1.4.1 Partial IO Mode Used
          2. 6.1.1.4.2 Partial IO Mode Unused
          3. 6.1.1.4.3 Data Sheet Reference for Power Sequence
          4. 6.1.1.4.4 Partial IO (Low-Power) Mode Checklist
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Supply Rails
        1. 6.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
        2. 6.1.2.2 Additional Information
          1. 6.1.2.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
        3. 6.1.2.3 Capacitors for Supply Rails Checklist
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI / MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI / WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
          4. 6.1.3.1.4 Additional Information
          5. 6.1.3.1.5 Clock Input Checklist - MCU_OSC0
          6. 6.1.3.1.6 Clock Input Checklist - WKUP_LFOSC0
        2. 6.1.3.2 Clock Outputs
          1. 6.1.3.2.1 Clock Output Checklist
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 External Reset Inputs
        2. 6.1.4.2 Reset Status Outputs
        3. 6.1.4.3 Additional Information
        4. 6.1.4.4 Processor Reset Input Checklist
        5. 6.1.4.5 Processor Reset Status Output Checklist
      5. 6.1.5 Configuration of Boot Modes (for Processor)
        1. 6.1.5.1 Processor Boot Mode Inputs Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Boot Mode Selection
          1. 6.1.5.2.1 Notes for USB Boot Mode
        3. 6.1.5.3 Boot Mode Implementation Approaches
        4. 6.1.5.4 Additional Information
        5. 6.1.5.5 Configuration of Boot Modes (for Processor) Checklist
    2. 6.2 Board Debug Using JTAG and EMU
      1. 6.2.1 JTAG and EMU Used
      2. 6.2.2 JTAG and EMU Not Used
      3. 6.2.3 Additional Information
      4. 6.2.4 Board Debug Using JTAG and EMU Checklist
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for IO Groups
      1. 7.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
      2. 7.1.2 Supply Connections for IO Groups Checklist
    2. 7.2 Memory Interface (DDRSS (DDR4/LPDDR4), MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
        2. 7.2.1.2 LPDDR4 SDRAM (Low-Power Double Data Rate 4 Synchronous Dynamic Random-Access Memory)
          1. 7.2.1.2.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
            1. 7.2.1.2.1.1 Memory Interface Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Resistors for Control and Calibration
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
            6. 7.2.1.2.1.6 LPDDR4 Implementation Checklist
      2. 7.2.2 Multi-Media Card/Secure Digital (MMCSD)
        1. 7.2.2.1 MMC0 - eMMC (Embedded Multi-Media Card) Interface
          1. 7.2.2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1 and AM62D-Q1
            1. 7.2.2.1.1.1 IO Power Supply
            2. 7.2.2.1.1.2 eMMC (Attached Device) Reset
            3. 7.2.2.1.1.3 Signals Connection
            4. 7.2.2.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.2.1.1.5 MMC0 (eMMC) Checklist
          2. 7.2.2.1.2 Additional Information on eMMC PHY
          3. 7.2.2.1.3 MMC0 – SD (Secure Digital) Card Interface
        2. 7.2.2.2 MMC1/MMC2 – SD (Secure Digital) Card Interface
          1. 7.2.2.2.1 IO Power Supply
          2. 7.2.2.2.2 SD Card Supply Reset and Boot Configuration
          3. 7.2.2.2.3 Signals Connection
          4. 7.2.2.2.4 ESD Protection
          5. 7.2.2.2.5 Capacitors for the Power Supply Rails
          6. 7.2.2.2.6 MMC1 SD Card Interface Checklist
        3. 7.2.2.3 MMC1 / MMC2 SDIO (Embedded) Interface
          1. 7.2.2.3.1 IO Power Supply
          2. 7.2.2.3.2 Signals Connection
          3. 7.2.2.3.3 MMC2 SDIO (Embedded) Interface Checklist
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) or Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 IO Power Supply
        2. 7.2.3.2 OSPI/QSPI Device Reset
        3. 7.2.3.3 Signals Connection
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
        7. 7.2.3.7 OSPI or QSPI Interface Implementation Checklist
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 IO Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Memory (Attached Device) Reset
        4. 7.2.4.4 Signals Connection
          1. 7.2.4.4.1 GPMC NAND
        5. 7.2.4.5 Capacitors for the Power Supply Rails
        6. 7.2.4.6 GPMC Interface Checklist
    3. 7.3 External Communication Interface (Ethernet (CPSW3G), USB2.0, UART and Controller Area Network (CAN))
      1. 7.3.1 Ethernet Interface Using CPSW3G (Common Platform Ethernet Switch 3-Port Gigabit)
        1. 7.3.1.1  IO Power Supply
        2. 7.3.1.2  Ethernet PHY Reset
        3. 7.3.1.3  Ethernet PHY Pin Strapping
        4. 7.3.1.4  Ethernet PHY (and MAC) Operation and Media Independent Interface (MII) Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5  MAC (Data, Control and Clock) Interface Signals Connection
        6. 7.3.1.6  External Interrupt (EXTINTn)
          1. 7.3.1.6.1 External Interrupt (EXTINTn) Checklist
        7. 7.3.1.7  MAC (Media Access Controller) to MAC Interface
        8. 7.3.1.8  MDIO (Management Data Input/Output) Interface
        9. 7.3.1.9  Ethernet MDI (Medium Dependent Interface) Including Magnetics
        10. 7.3.1.10 Capacitors for the Power Supply Rails
        11. 7.3.1.11 Ethernet Interface Checklist
      2. 7.3.2 Universal Serial Bus (USB2.0)
        1. 7.3.2.1 USBn (n = 0-1) Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
          4. 7.3.2.1.4 USB Type-C®
        2. 7.3.2.2 USBn (n = 0-1) Not Used
        3. 7.3.2.3 Additional Information
        4. 7.3.2.4 USB Interface Checklist
      3. 7.3.3 Universal Asynchronous Receiver/Transmitter (UART)
        1. 7.3.3.1 Universal Asynchronous Receiver/Transmitter (UART) Checklist
      4. 7.3.4 Controller Area Network (CAN)
        1. 7.3.4.1 Controller Area Network Checklist
    4. 7.4 On-board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
        1. 7.4.1.1 MCSPI Checklist
        2. 7.4.1.2 MCASP Checklist
      2. 7.4.2 Inter-Integrated Circuit (I2C)
        1. 7.4.2.1 I2C (Open-drain Output Type Buffer) Interface Checklist
        2. 7.4.2.2 I2C (Emulated Open-drain Output Type Buffer) Interface Checklist
    5. 7.5 User Interface (CSIRX0, DPI), GPIO and Hardware Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
        3. 7.5.1.3 CSIRX0 Checklist
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 Display Parallel Interface (DPI)
          1. 7.5.2.1.1 AM62A7 / AM62A3 / AM62A7-Q1 / AM62A3-Q1
            1. 7.5.2.1.1.1 IO Power Supply
            2. 7.5.2.1.1.2 DPI (Attached Device) Reset
            3. 7.5.2.1.1.3 Connection
            4. 7.5.2.1.1.4 Signals Connection
            5. 7.5.2.1.1.5 Capacitors for the Power Supply Rails
            6. 7.5.2.1.1.6 DPI (VOUT0) Checklist
          2. 7.5.2.1.2 AM62D-Q1
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 Availability of CLKOUT on Processor GPIO
        2. 7.5.3.2 Connection and External Buffering
        3. 7.5.3.3 Additional Information
        4. 7.5.3.4 GPIO Checklist
      4. 7.5.4 On-board Hardware Diagnostics
        1. 7.5.4.1 Monitoring of On-board Supply Voltages Using Processor Voltage Monitors
          1. 7.5.4.1.1 Voltage Monitor Pins Used
            1. 7.5.4.1.1.1 Voltage Monitor Checklist
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Internal Temperature Monitoring
          1. 7.5.4.2.1 Internal Temperature Monitoring Checklist
        3. 7.5.4.3 Connection of Error Signal Output (MCU_ERRORn)
        4. 7.5.4.4 High Frequency Oscillator (MCU_OSC0) Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Processor Pin Configuration Using PinMux Tool
      2. 7.6.2 Schematics Configurations
      3. 7.6.3 Connecting Supply Rails to Pullups
      4. 7.6.4 Peripheral (Subsystem) Clock Outputs
      5. 7.6.5 General Board Bring-up and Debug
        1. 7.6.5.1 Clock Output for Board Bring-Up, Test, or Debug
        2. 7.6.5.2 Additional Information
        3. 7.6.5.3 General Board Bring-up and Debug Checklist
  11. 8 Self-Review of the Custom Board Schematics Design
  12. 9 Layout Notes (Added on the Schematic)
    1. 9.1 Layout Checklist
  13. 10Custom Board Design Simulation
  14. 11Additional References
    1. 11.1 FAQ Covering AM6xx Processor Family
    2. 11.2 FAQs - Processor Product Family Wise and Sitara Processor Families
    3. 11.3 Processor Attached Devices
  15. 12Summary
  16. 13References
    1. 13.1 AM62A7, AM62A3, AM62A7-Q1, AM62A3-Q1
    2. 13.2 AM62D-Q1
    3. 13.3 AM62P, AM62P-Q1
    4. 13.4 AM625, AM623, AM625SIP, AM625-Q1, AM620-Q1
    5. 13.5 Common for all Processor Families
    6. 13.6 Master List of Available FAQs - Processor Family Wise
    7. 13.7 Master List of Available FAQs - Sitara Processor Families
    8. 13.8 FAQs Including Software Related
    9. 13.9 FAQs for Attached Devices
  17. 14Terminology
  18. 15Revision History

7.5.3.4 GPIO Checklist

General

Review and verify the following for the custom schematic design:

  1. Above sections, including relevant application notes and FAQ links.
  2. Pin connectivity requirements and pin attributes.
  3. Electrical characteristics and any additional available information.
  4. Input signal applied to the processor LVCMOS inputs follow the slew rate requirements. Connecting a capacitor directly at the input increases the signal slew and is not recommended.
  5. Connection of capacitor load directly to the processor output for control or enabling of attached device is not allowed (recommend simulation when capacitor load > 22pF (place holder) is used).
  6. All IO pins referenced to VDDSHVx or VDDSHV_MCU or VDDSHV_CANUART connect to one voltage level. Each IO has an associated supply voltage used to power the IO cell (VDDSHVx). If VDDSHVx is sourced from 3.3V (1.8V) supply, all IO referenced to VDDSHVx rail operate at 3.3V (1.8V) levels.
  7. No input voltage applied to the processor IOs before the VDDSHVx supply ramps (excluding fail-safe IOs). Most processor IOs are not fail-safe. Applying voltage to the IOs is not recommended or allowed, while the corresponding IO supply for IO group (VDDSHVx) is off. Fail-safe IOs include MCU_PORz, WKUP_I2C0_SCL, WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn, and USB0-1_VBUS, when a recommended VBUS divider is used.
  8. One of the common use case for the IO interface is driving LEDs for indication. The designer can review the LED source or sink current and the effect on the voltage level and adjust the LED current accordingly.
  9. Shorting of multiple IOs together directly is not recommended.
  10. Pad configuration based on the required IO direction.
  11. Directly connecting processor IOs with alternate functions to supply or VSS is not recommended or allowed, including boot mode inputs. The board designer can have errors with the firmware and miss-configure the LVCMOS GPIOs that are intended as inputs, to be outputs driving logic high instead.

Schematic Review

Follow the below list for the custom schematic design:

  1. Pulls are added for any of the processor or attached device IOs that can float.
  2. Pullups are connected to the same IO supply for IO group VDDSHVx referenced by the IOs.
  3. The supply voltage for all pullups that are connected to processor IOs matches the voltage applied to the corresponding IO supply for IO group (VDDSHVx). Pulling a signal to a different IO voltage can cause voltage leakage.
  4. IO level compatibility for externally applied inputs from a add-on or carrier board or through an external connector
  5. Supply rails connected follow the ROC.

Additional

  1. Common processor LVCMOS IO interface guidelines, refer to Section 7.5.3.2.
    • Most of the processor IOs are not fail-safe. This is not recommended or allowed to apply input before supply ramps.
    • Processor LVCMOS IOs have slew rate requirements specified, applying a slow ramp input or connecting a capacitor directly at the input is not recommended.
    • Connecting a capacitor load > 22pF (place holder) at the output is not recommended. DNI capacitor or perform simulations based on the use case.
    • Processor IO buffers are off during reset. A pull is recommended near to the attached device being driven by the processor IO that can float.
  2. A parallel pull is recommended for any processor IO pad that has a trace connected. When adding pull is not feasible, route the traces away from noisy signals. Processor IO buffers are off during reset. A pullup is recommended near to the attached device, to hold the attached device IO inputs that can float in a known state. Use of pulls are attached device dependent.
  3. IO compatibility and fail-safe operation between the processor IOs and attached devices connected through IOs.
  4. Fail-safe operation when connected to external signals. Applying an external input before supply ramps cold causes voltage feed and affects the processor performance.
  5. Capacitor loading of the processor output (when capacitor value > 22pF (place holder) is connected, designer must simulate), slew of the input signal (LVCMOS input slew is 1000ns or less).
  6. IO current sink or source follows the data sheet recommendations.
  7. External ESD protection is provided when the IOs connect directly to external interface signals.